From 65200be7fe6aba9f9a9b8f9e00fcab12fdca5ccd Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 4 Mar 2017 07:33:45 +0200 Subject: bap/ode_e20XX: Switch away from AGESA_LEGACY_WRAPPER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ia747b3bc149a672a6de2ecf0308141172321a493 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/20717 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 54 +++++++++--------------------- src/mainboard/bap/ode_e20XX/Kconfig | 1 - src/mainboard/bap/ode_e20XX/OemCustomize.c | 35 ++++++++++--------- src/mainboard/bap/ode_e20XX/mainboard.c | 5 +-- 4 files changed, 36 insertions(+), 59 deletions(-) (limited to 'src/mainboard/bap') diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index e6773b8d5f..ac6e1471aa 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -16,6 +16,7 @@ #include "AGESA.h" #include "amdlib.h" #include +#include #include "Ids.h" #include "heapManager.h" #include "FchPlatform.h" @@ -26,7 +27,6 @@ #include #include -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); const BIOS_CALLOUT_STRUCT BiosCallouts[] = @@ -38,7 +38,6 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = {AGESA_GET_IDS_INIT_DATA, agesa_EmptyIdsInitData }, {AGESA_HOOKBEFORE_DQS_TRAINING, agesa_NoopSuccess }, {AGESA_HOOKBEFORE_EXIT_SELF_REF, agesa_NoopSuccess }, - {AGESA_FCH_OEM_CALLOUT, Fch_Oem_config }, {AGESA_GNB_GFX_GET_VBIOS_IMAGE, agesa_GfxGetVbiosImage } }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); @@ -179,44 +178,21 @@ static void oem_fan_control(FCH_DATA_BLOCK *FchParams) #endif /* CONFIG_HUDSON_IMC_FWM */ } -/** - * Fch Oem setting callback - * - * Configure platform specific Hudson device, - * such Azalia, SATA, IMC etc. - */ -static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) +void board_FCH_InitReset(struct sysinfo *cb_NA, FCH_RESET_DATA_BLOCK *FchParams_reset) +{ +} + +void board_FCH_InitEnv(struct sysinfo *cb_NA, FCH_DATA_BLOCK *FchParams_env) { - AMD_CONFIG_PARAMS *StdHeader = ConfigPtr; - - if (StdHeader->Func == AMD_INIT_RESET) { - FCH_RESET_DATA_BLOCK *FchParams_reset = (FCH_RESET_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT RESET "); - //FchParams_reset->EcChannel0 = TRUE; /* logical devicd 3 */ - FchParams_reset->FchReset.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams_reset->FchReset.Xhci1Enable = FALSE; - } else if (StdHeader->Func == AMD_INIT_ENV) { - FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; - printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); - - /* Azalia Controller OEM Codec Table Pointer */ - FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); - /* Azalia Controller Front Panel OEM Table Pointer */ - - /* Fan Control */ - oem_fan_control(FchParams_env); - - /* XHCI configuration */ - FchParams_env->Usb.Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); - FchParams_env->Usb.Xhci1Enable = FALSE; - - /* sata configuration */ - /* disable GEN2 limitation */ - FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE; - } - printk(BIOS_DEBUG, "Done\n"); - - return AGESA_SUCCESS; + /* Azalia Controller OEM Codec Table Pointer */ + FchParams_env->Azalia.AzaliaOemCodecTablePtr = (CODEC_TBL_LIST *)(&CodecTableList[0]); + + /* Fan Control */ + oem_fan_control(FchParams_env); + + /* sata configuration */ + /* disable GEN2 limitation */ + FchParams_env->Sata.SataMode.SataSetMaxGen2 = FALSE; } static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ea9fec5aba..6631ac8d71 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -18,7 +18,6 @@ if BOARD_ODE_E20XX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select AGESA_LEGACY_WRAPPER select CPU_AMD_AGESA_FAMILY16_KB select NORTHBRIDGE_AMD_AGESA_FAMILY16_KB select SOUTHBRIDGE_AMD_AGESA_YANGTZE diff --git a/src/mainboard/bap/ode_e20XX/OemCustomize.c b/src/mainboard/bap/ode_e20XX/OemCustomize.c index 752293a031..00d51b6b27 100644 --- a/src/mainboard/bap/ode_e20XX/OemCustomize.c +++ b/src/mainboard/bap/ode_e20XX/OemCustomize.c @@ -20,7 +20,7 @@ #include #include "Filecode.h" -#include +#include #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE @@ -89,6 +89,13 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = DdiList }; +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + FCH_RESET_INTERFACE *FchReset = &Reset->FchInterface; + FchReset->Xhci0Enable = IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE); + FchReset->Xhci1Enable = FALSE; +} + /*---------------------------------------------------------------------------------------*/ /** * OemCustomizeInitEarly @@ -105,7 +112,7 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { **/ /*---------------------------------------------------------------------------------------*/ -static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) +void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { AGESA_STATUS Status; PCIe_COMPLEX_DESCRIPTOR *PcieComplexListPtr; @@ -127,14 +134,6 @@ static AGESA_STATUS OemInitEarly(AMD_EARLY_PARAMS * InitEarly) PcieComplexListPtr = (PCIe_COMPLEX_DESCRIPTOR *) AllocHeapParams.BufferPtr; LibAmdMemCopy (PcieComplexListPtr, &PcieComplex, sizeof(PcieComplex), &InitEarly->StdHeader); InitEarly->GnbConfig.PcieComplexList = PcieComplexListPtr; - return AGESA_SUCCESS; -} - -static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) -{ - /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ - InitMid->GnbMidConfiguration.iGpuVgaMode = 0; - return AGESA_SUCCESS; } /*---------------------------------------------------------------------------------------- @@ -148,7 +147,7 @@ static AGESA_STATUS OemInitMid(AMD_MID_PARAMS * InitMid) * is populated, AGESA will base its settings on the data from the table. Otherwise, it will * use its default conservative settings. */ -CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { +static CONST PSO_ENTRY ROMDATA PlatformMemoryTable[] = { #define SEED_WL 0x0E WRITE_LEVELING_SEED( @@ -174,7 +173,13 @@ CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = { PSO_END }; -const struct OEM_HOOK OemCustomize = { - .InitEarly = OemInitEarly, - .InitMid = OemInitMid, -}; +void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *InitPost) +{ + InitPost->MemConfig.PlatformMemoryConfiguration = (PSO_ENTRY *)PlatformMemoryTable; +} + +void board_BeforeInitMid(struct sysinfo *cb, AMD_MID_PARAMS *InitMid) +{ + /* 0 iGpuVgaAdapter, 1 iGpuVgaNonAdapter; */ + InitMid->GnbMidConfiguration.iGpuVgaMode = 0; +} diff --git a/src/mainboard/bap/ode_e20XX/mainboard.c b/src/mainboard/bap/ode_e20XX/mainboard.c index bc161de8ab..7e729f0c06 100644 --- a/src/mainboard/bap/ode_e20XX/mainboard.c +++ b/src/mainboard/bap/ode_e20XX/mainboard.c @@ -28,7 +28,7 @@ #include #include #include -#include +#include /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -120,9 +120,6 @@ static void mainboard_enable(device_t dev) { printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); - if (acpi_is_wakeup_s3()) - agesawrapper_fchs3earlyrestore(); - /* Initialize the PIRQ data structures for consumption */ pirq_setup(); } -- cgit v1.2.3