From 486c05f4bfea71b6a5cbb216272199b2ad1dca02 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 17 Jan 2015 18:08:40 +0200 Subject: AMD cimx/sb800: Fix PCI-to-PCI bridge 0:14.4 configuration MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit A set of pins can be configured for GPIO or (parallel) PCI bridge use. When requested configuration is 0:14.4 enabled, register programming must be done before attempting to enumerate devices behind the bridge. When requested configuration is 0:14.4 disabled, we must not even temporarily enable pins for PCI use to avoid spurious GPIO state changes. As our PCI subsystem currently does not configure visible PCI bridges that are marked disabled, we cannot mark 0:14.4 disabled just yet but need to handle pcengines/apu1 as a special case. Drop related dead code. Change-Id: I8644ebae43b33121ef2a7ed30f745299716ce0df Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/8329 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel Reviewed-by: Felix Held Reviewed-by: Alexandru Gagniuc --- src/mainboard/avalue/eax-785e/mainboard.c | 4 ---- 1 file changed, 4 deletions(-) (limited to 'src/mainboard/avalue/eax-785e') diff --git a/src/mainboard/avalue/eax-785e/mainboard.c b/src/mainboard/avalue/eax-785e/mainboard.c index 6ce3469e78..0f5f7446a8 100644 --- a/src/mainboard/avalue/eax-785e/mainboard.c +++ b/src/mainboard/avalue/eax-785e/mainboard.c @@ -37,10 +37,6 @@ void enable_int_gfx(void) { volatile u8 *gpio_reg; -#ifdef UNUSED_CODE - RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */ - RWPMIO(SB_PMIOA_REGF6, AccWidthUint8, ~(BIT0), BIT0); /* Disable Gec */ -#endif /* make sure the Acpi MMIO(fed80000) is accessible */ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0); -- cgit v1.2.3