From f8ee1806ac524bc782c93eccc59ee3c929abddb9 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Fri, 18 Jan 2008 15:08:58 +0000 Subject: Rename almost all occurences of LinuxBIOS to coreboot. Due to the automatic nature of this update, I am self-acking. It worked in abuild. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3053 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asus/a8n_e/Config.lb | 14 +++++++------- src/mainboard/asus/a8n_e/Options.lb | 14 +++++++------- src/mainboard/asus/a8v-e_se/Config.lb | 14 +++++++------- src/mainboard/asus/a8v-e_se/Options.lb | 14 +++++++------- src/mainboard/asus/mew-am/Options.lb | 2 +- src/mainboard/asus/mew-vm/Config.lb | 14 +++++++------- src/mainboard/asus/mew-vm/Options.lb | 10 +++++----- src/mainboard/asus/p2b-f/Options.lb | 2 +- src/mainboard/asus/p2b/Options.lb | 2 +- src/mainboard/asus/p3b-f/Options.lb | 2 +- 10 files changed, 44 insertions(+), 44 deletions(-) (limited to 'src/mainboard/asus') diff --git a/src/mainboard/asus/a8n_e/Config.lb b/src/mainboard/asus/a8n_e/Config.lb index db635e52d4..07a7ade1aa 100644 --- a/src/mainboard/asus/a8n_e/Config.lb +++ b/src/mainboard/asus/a8n_e/Config.lb @@ -23,7 +23,7 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FAILOVER_IMAGE default ROM_SECTION_SIZE = FAILOVER_SIZE @@ -39,18 +39,18 @@ else end ## -## Compute the start location and size size of the LinuxBIOS bootloader. +## Compute the start location and size size of the coreboot bootloader. ## default PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) ## -## Compute where this copy of LinuxBIOS will start in the boot ROM. +## Compute where this copy of coreboot will start in the boot ROM. ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can be cached to speed up LinuxBIOS +## Compute a range of ROM that can be cached to speed up coreboot ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2 (here 64 Kbyte) @@ -106,7 +106,7 @@ if USE_DCACHE_RAM end ## -## Build our 16 bit and 32 bit LinuxBIOS entry code. +## Build our 16 bit and 32 bit coreboot entry code. ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -130,7 +130,7 @@ if USE_DCACHE_RAM end ## -## Build our reset vector (this is where LinuxBIOS is entered). +## Build our reset vector (this is where coreboot is entered). ## if HAVE_FAILOVER_BOOT if USE_FAILOVER_IMAGE @@ -186,7 +186,7 @@ end ### -### This is the early phase of LinuxBIOS startup. +### This is the early phase of coreboot startup. ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/asus/a8n_e/Options.lb b/src/mainboard/asus/a8n_e/Options.lb index 392c0bc1b4..e4eef79986 100644 --- a/src/mainboard/asus/a8n_e/Options.lb +++ b/src/mainboard/asus/a8n_e/Options.lb @@ -59,7 +59,7 @@ uses MAINBOARD_VENDOR uses MAINBOARD uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -127,7 +127,7 @@ default HAVE_FALLBACK_BOOT=1 default HAVE_FAILOVER_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=1 @@ -149,7 +149,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=1 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -223,10 +223,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x10f1 default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2891 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = (64*1024) #65536 @@ -247,7 +247,7 @@ default HEAP_SIZE=0x4000 default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE ) ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -296,7 +296,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/asus/a8v-e_se/Config.lb b/src/mainboard/asus/a8v-e_se/Config.lb index a8b1a1c3bc..e95511a647 100644 --- a/src/mainboard/asus/a8v-e_se/Config.lb +++ b/src/mainboard/asus/a8v-e_se/Config.lb @@ -23,7 +23,7 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -35,19 +35,19 @@ ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default CONFIG_ROM_PAYLOAD = 1 ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -97,7 +97,7 @@ if USE_DCACHE_RAM end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## if USE_FALLBACK_IMAGE @@ -122,7 +122,7 @@ end ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE @@ -141,7 +141,7 @@ if USE_DCACHE_RAM end ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/asus/a8v-e_se/Options.lb b/src/mainboard/asus/a8v-e_se/Options.lb index 6c57edecdb..b6c5cea799 100644 --- a/src/mainboard/asus/a8v-e_se/Options.lb +++ b/src/mainboard/asus/a8v-e_se/Options.lb @@ -56,7 +56,7 @@ uses MAINBOARD_PART_NUMBER uses MAINBOARD_VENDOR uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses _RAMBASE uses CONFIG_GDB_STUB uses CROSS_COMPILE @@ -121,7 +121,7 @@ default FALLBACK_SIZE=256 * 1024 default HAVE_FALLBACK_BOOT=1 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET=0 @@ -143,7 +143,7 @@ default HAVE_MP_TABLE=1 default HAVE_OPTION_TABLE=0 ## -## Move the default LinuxBIOS cmos range off of AMD RTC registers +## Move the default coreboot cmos range off of AMD RTC registers ## default LB_CKS_RANGE_START=49 default LB_CKS_RANGE_END=122 @@ -217,10 +217,10 @@ default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1043 #default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x1234 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 64 * 1024 ## @@ -242,7 +242,7 @@ default HEAP_SIZE=256 * 1024 ##default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE ## -## LinuxBIOS C code runs at this location in RAM +## Coreboot C code runs at this location in RAM ## default _RAMBASE=0x00004000 @@ -291,7 +291,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/asus/mew-am/Options.lb b/src/mainboard/asus/mew-am/Options.lb index b02013191d..d4cf5e307f 100644 --- a/src/mainboard/asus/mew-am/Options.lb +++ b/src/mainboard/asus/mew-am/Options.lb @@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE diff --git a/src/mainboard/asus/mew-vm/Config.lb b/src/mainboard/asus/mew-vm/Config.lb index ade4ffd1ec..76a74a3425 100644 --- a/src/mainboard/asus/mew-vm/Config.lb +++ b/src/mainboard/asus/mew-vm/Config.lb @@ -1,6 +1,6 @@ ## ## Compute the location and size of where this firmware image -## (linuxBIOS plus bootloader) will live in the boot rom chip. +## (coreboot plus bootloader) will live in the boot rom chip. ## if USE_FALLBACK_IMAGE default ROM_SECTION_SIZE = FALLBACK_SIZE @@ -12,18 +12,18 @@ end ## ## Compute the start location and size size of -## The linuxBIOS bootloader. +## The coreboot bootloader. ## default CONFIG_ROM_PAYLOAD_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1) default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE ) ## -## Compute where this copy of linuxBIOS will start in the boot rom +## Compute where this copy of coreboot will start in the boot rom ## default _ROMBASE = ( CONFIG_ROM_PAYLOAD_START + PAYLOAD_SIZE ) ## -## Compute a range of ROM that can cached to speed up linuxBIOS, +## Compute a range of ROM that can cached to speed up coreboot, ## execution speed. ## ## XIP_ROM_SIZE must be a power of 2. @@ -70,7 +70,7 @@ makerule ./auto.inc end ## -## Build our 16 bit and 32 bit linuxBIOS entry code +## Build our 16 bit and 32 bit coreboot entry code ## mainboardinit cpu/x86/16bit/entry16.inc mainboardinit cpu/x86/32bit/entry32.inc @@ -78,7 +78,7 @@ ldscript /cpu/x86/16bit/entry16.lds ldscript /cpu/x86/32bit/entry32.lds ## -## Build our reset vector (This is where linuxBIOS is entered) +## Build our reset vector (This is where coreboot is entered) ## if USE_FALLBACK_IMAGE mainboardinit cpu/x86/16bit/reset16.inc @@ -98,7 +98,7 @@ mainboardinit arch/i386/lib/id.inc ldscript /arch/i386/lib/id.lds ### -### This is the early phase of linuxBIOS startup +### This is the early phase of coreboot startup ### Things are delicate and we test to see if we should ### failover to another image. ### diff --git a/src/mainboard/asus/mew-vm/Options.lb b/src/mainboard/asus/mew-vm/Options.lb index 3f8775f2e6..da63cffd9e 100644 --- a/src/mainboard/asus/mew-vm/Options.lb +++ b/src/mainboard/asus/mew-vm/Options.lb @@ -10,7 +10,7 @@ uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE @@ -60,7 +60,7 @@ default HAVE_FALLBACK_BOOT = 1 default HAVE_MP_TABLE = 0 ## -## Build code to reset the motherboard from linuxBIOS +## Build code to reset the motherboard from coreboot ## default HAVE_HARD_RESET = 0 @@ -79,10 +79,10 @@ default HAVE_OPTION_TABLE = 0 default CONFIG_IDE = 1 ### -### LinuxBIOS layout values +### coreboot layout values ### -## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy. +## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy. default ROM_IMAGE_SIZE = 65536 default FALLBACK_SIZE = 131072 @@ -138,7 +138,7 @@ default TTYS0_BASE=0x3f8 default TTYS0_LCS=0x3 ## -### Select the linuxBIOS loglevel +### Select the coreboot loglevel ## ## EMERG 1 system is unusable ## ALERT 2 action must be taken immediately diff --git a/src/mainboard/asus/p2b-f/Options.lb b/src/mainboard/asus/p2b-f/Options.lb index df13ee490b..ce083410e4 100644 --- a/src/mainboard/asus/p2b-f/Options.lb +++ b/src/mainboard/asus/p2b-f/Options.lb @@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE diff --git a/src/mainboard/asus/p2b/Options.lb b/src/mainboard/asus/p2b/Options.lb index 8653db38aa..4038c3c7d5 100644 --- a/src/mainboard/asus/p2b/Options.lb +++ b/src/mainboard/asus/p2b/Options.lb @@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE diff --git a/src/mainboard/asus/p3b-f/Options.lb b/src/mainboard/asus/p3b-f/Options.lb index df13ee490b..ce083410e4 100644 --- a/src/mainboard/asus/p3b-f/Options.lb +++ b/src/mainboard/asus/p3b-f/Options.lb @@ -30,7 +30,7 @@ uses IRQ_SLOT_COUNT uses MAINBOARD uses MAINBOARD_VENDOR uses MAINBOARD_PART_NUMBER -uses LINUXBIOS_EXTRA_VERSION +uses COREBOOT_EXTRA_VERSION uses ARCH uses FALLBACK_SIZE uses STACK_SIZE -- cgit v1.2.3