From e52738b42889a8bf6b96fe86b87fbdd73947b367 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Thu, 21 Sep 2017 12:32:43 +0300 Subject: AGESA binaryPI boards: Fix some whitespace MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/mainboard/asus/f2a85-m/OemCustomize.c | 44 +++++++++++++++---------------- 1 file changed, 22 insertions(+), 22 deletions(-) (limited to 'src/mainboard/asus') diff --git a/src/mainboard/asus/f2a85-m/OemCustomize.c b/src/mainboard/asus/f2a85-m/OemCustomize.c index 316a110991..5ecba8ee6a 100644 --- a/src/mainboard/asus/f2a85-m/OemCustomize.c +++ b/src/mainboard/asus/f2a85-m/OemCustomize.c @@ -67,24 +67,24 @@ * 38 DP2_TX[P,N]6 */ -static const PCIe_PORT_DESCRIPTOR PortList [] = { +static const PCIe_PORT_DESCRIPTOR PortList[] = { /* PCIe port, Lanes 8:23, PCI Device Number 2, blue x16 slot */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 4:7, PCI Device Number 4, black x16 slot (in fact x4) */ { 0, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 4, 7), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) }, /* PCIe port, Lanes 0:3, UMI link to SB, PCI Device Number 8 */ { DESCRIPTOR_TERMINATE_LIST, - PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) }, }; @@ -94,24 +94,24 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { * Tested and works: VGA/DVI * Untested: HDMI */ -static const PCIe_DDI_DESCRIPTOR DdiList [] = { +static const PCIe_DDI_DESCRIPTOR DdiList[] = { // DP0 to HDMI0/DP { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 24, 27), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux1, Hdp1) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 24, 27), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux1, Hdp1) }, // DP1 to FCH { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 28, 31), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeNutmegDpToVga, Aux2, Hdp2) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 28, 31), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeNutmegDpToVga, Aux2, Hdp2) }, // DP2 to HDMI1/DP { 0, - PCIE_ENGINE_DATA_INITIALIZER (PcieDdiEngine, 32, 35), - PCIE_DDI_DATA_INITIALIZER (ConnectorTypeHDMI, Aux3, Hdp3) + PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), + PCIE_DDI_DATA_INITIALIZER(ConnectorTypeHDMI, Aux3, Hdp3) }, }; @@ -211,22 +211,22 @@ void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) */ static CONST PSO_ENTRY ROMDATA MemoryTable_M[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 2), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 2), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), /* TODO: is this OK for DDR3 socket FM2? - MEMCLK_DIS_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), - CKE_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), - ODT_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), - CS_TRI_MAP (ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), + CKE_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x05, 0x0A), + ODT_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00), + CS_TRI_MAP(ANY_SOCKET, ANY_CHANNEL, 0x01, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00), */ PSO_END }; static CONST PSO_ENTRY ROMDATA MemoryTable_M_LE[] = { - NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 1), - NUMBER_OF_CHANNELS_SUPPORTED (ANY_SOCKET, 2), + NUMBER_OF_DIMMS_SUPPORTED(ANY_SOCKET, ANY_CHANNEL, 1), + NUMBER_OF_CHANNELS_SUPPORTED(ANY_SOCKET, 2), PSO_END }; -- cgit v1.2.3