From d07048a7f932aa779dc64d7c503df121c2a76f0b Mon Sep 17 00:00:00 2001
From: Elyes HAOUAS <ehaouas@noos.fr>
Date: Sun, 21 Apr 2019 20:17:11 +0200
Subject: src/mb: Use system_reset()

Use already defined system_reset() function.

Change-Id: I68ff4cffa2bfab6a15299795c3e1837fc9b85806
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32379
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/mainboard/asus/p5gc-mx/romstage.c  | 4 ++--
 src/mainboard/asus/p5qpl-am/romstage.c | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

(limited to 'src/mainboard/asus')

diff --git a/src/mainboard/asus/p5gc-mx/romstage.c b/src/mainboard/asus/p5gc-mx/romstage.c
index 6727f4ab88..beb276c7da 100644
--- a/src/mainboard/asus/p5gc-mx/romstage.c
+++ b/src/mainboard/asus/p5gc-mx/romstage.c
@@ -19,6 +19,7 @@
 
 #include <stdint.h>
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
@@ -214,8 +215,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	if (!s3resume && setup_sio_gpio(c_bsel)) {
 		printk(BIOS_DEBUG,
 			"Needs reset to configure CPU BSEL straps\n");
-		outb(0xe, 0xcf9);
-		halt();
+		full_reset();
 	}
 
 	/* Enable SPD ROMs and DDR-II DRAM */
diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c
index 8ce5979998..4174981ac2 100644
--- a/src/mainboard/asus/p5qpl-am/romstage.c
+++ b/src/mainboard/asus/p5qpl-am/romstage.c
@@ -16,6 +16,7 @@
  */
 
 #include <arch/io.h>
+#include <cf9_reset.h>
 #include <device/pnp_ops.h>
 #include <device/pci_ops.h>
 #include <console/console.h>
@@ -191,8 +192,7 @@ void mainboard_romstage_entry(unsigned long bist)
 	if (!s3_resume && setup_sio_gpio()) {
 		printk(BIOS_DEBUG,
 		       "Needs reset to configure CPU BSEL straps\n");
-		outb(0xe, 0xcf9);
-		halt();
+		full_reset();
 	}
 
 	sdram_initialize(boot_path, spd_addrmap);
-- 
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