From c36b5ea18983e3dbb021ae3012698d1357dcdf66 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Mon, 5 Feb 2024 16:11:26 -0500 Subject: mb/*: Copy bd82x6x boards' USB port config into devicetree For mainboards using southbridge/intel/bd82x6x, copy the contents of mainboard_usb_ports array into southbridge devicetree. In-line comments are maintained. Boards also capable of using MRC raminit are done in a separate patch. Change-Id: Ia8a967eb3466106f3a34e024260e13d02f449a25 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/81879 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/asus/h61-series/devicetree.cb | 16 ++++++++++++++++ src/mainboard/asus/maximus_iv_gene-z/devicetree.cb | 17 +++++++++++++++++ .../asus/p8x7x-series/variants/p8c_ws/overridetree.cb | 16 ++++++++++++++++ .../asus/p8x7x-series/variants/p8h77-v/overridetree.cb | 16 ++++++++++++++++ .../p8x7x-series/variants/p8z77-v_lx2/overridetree.cb | 17 +++++++++++++++++ 5 files changed, 82 insertions(+) (limited to 'src/mainboard/asus') diff --git a/src/mainboard/asus/h61-series/devicetree.cb b/src/mainboard/asus/h61-series/devicetree.cb index 7f37acc7ca..365b5ed4e9 100644 --- a/src/mainboard/asus/h61-series/devicetree.cb +++ b/src/mainboard/asus/h61-series/devicetree.cb @@ -11,6 +11,22 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x33" register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" device ref mei1 on end device ref mei2 off end diff --git a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb index 2642fbd68b..79213c41a0 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb +++ b/src/mainboard/asus/maximus_iv_gene-z/devicetree.cb @@ -15,6 +15,23 @@ chip northbridge/intel/sandybridge register "spi_lvscc" = "0x2005" register "spi_uvscc" = "0x2005" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 }, + { 1, 0, 6 } + }" + device ref mei1 on end device ref mei2 off end device ref me_ide_r off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb index 4b7bb1c75e..1e8d807669 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8c_ws/overridetree.cb @@ -7,6 +7,22 @@ chip northbridge/intel/sandybridge subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x register "gen1_dec" = "0x000c0291" + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" device ref pcie_rp1 on end # PCIEX16_4 (electrical x4) device ref pcie_rp2 off end device ref pcie_rp3 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb index dbf1f359b5..1389304671 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8h77-v/overridetree.cb @@ -4,6 +4,22 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } + }" register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) device ref pcie_rp2 off end diff --git a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb index 0ae41b3acc..66bc5bb180 100644 --- a/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb +++ b/src/mainboard/asus/p8x7x-series/variants/p8z77-v_lx2/overridetree.cb @@ -4,6 +4,23 @@ chip northbridge/intel/sandybridge device domain 0 on subsystemid 0x1043 0x84ca inherit chip southbridge/intel/bd82x6x + register "usb_port_config" = "{ + { 1, 0, 0 }, + { 1, 0, 0 }, + { 1, 0, 1 }, + { 1, 0, 1 }, + { 1, 0, 2 }, + { 1, 0, 2 }, + { 1, 0, 3 }, + { 1, 0, 3 }, + { 1, 0, 4 }, + { 1, 0, 4 }, + { 1, 0, 6 }, + { 1, 0, 5 }, + { 1, 0, 5 }, + { 1, 0, 6 } +}" + register "gen1_dec" = "0x000c0291" device ref pcie_rp1 on end # PCIEX16_2 (electrical x4) -- cgit v1.2.3