From 65ddbb720b1d5e7bcf32a3e112f06f5afbeb1100 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 19 May 2018 17:42:49 +0200 Subject: mb/asus/p8h61-m_pro: Add new mainboard Tested with GRUB 2.02 as a payload, booting Arch Linux as well as Debian. This code is based on the output of autoport as well as other mainboards supported in coreboot already. Working: - Serial port I/O - S3 suspend/resume. Untested with SeaBIOS since it failed to resume on a similar board. It is likely to be due to low memory corruption, but I have not worked on it. - USB ports and headers - USB3 ports attached to the ASM1042 controller. SeaBIOS can boot from them, and it is likely GRUB can detect devices on those ports as well. The chip has a small SPI flash nearby, which seems to hold an Option ROM. - Gigabit Ethernet - Integrated graphics (libgfxinit) - VGA BIOS for integrated graphics init - PCIe x16 graphics - PCIe x1 - SATA controller - Hardware Monitor - Fan Control (fancontrol on linux works well) - Native raminit - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. - NVRAM settings. Only debug_level has been tested. Untested: - DVI port. It can detect a "fake" display, that is, an EEPROM connected to the DVI port. Thus, gma-mainboard.ads has been setup accordingly. - PS/2 port. - Audio: Only rear output (green) has been tested. - EHCI debug. - Parallel port header. - Non-Linux OSes - ACPI thermal zone and fan control (probably not working) Not working: - Booting from devices attached to the ASM1061 controller. Devices on ports work fine once Linux has loaded. - Any SATA devices with Tianocore (payload issue) Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/26419 Reviewed-by: Nico Huber Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/asus/p8h61-m_pro/devicetree.cb | 126 +++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) create mode 100644 src/mainboard/asus/p8h61-m_pro/devicetree.cb (limited to 'src/mainboard/asus/p8h61-m_pro/devicetree.cb') diff --git a/src/mainboard/asus/p8h61-m_pro/devicetree.cb b/src/mainboard/asus/p8h61-m_pro/devicetree.cb new file mode 100644 index 0000000000..04dc68b3e8 --- /dev/null +++ b/src/mainboard/asus/p8h61-m_pro/devicetree.cb @@ -0,0 +1,126 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2018 Angel Pons +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +chip northbridge/intel/sandybridge + register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410 }" + register "gfx.ndid" = "3" + device cpu_cluster 0x0 on + chip cpu/intel/socket_LGA1155 + device lapic 0x0 on + end + end + chip cpu/intel/model_206ax + register "c1_acpower" = "1" + register "c1_battery" = "1" + register "c2_acpower" = "3" + register "c2_battery" = "3" + register "c3_acpower" = "5" + register "c3_battery" = "5" + device lapic 0xacac off + end + end + end + register "pci_mmio_size" = "2048" + device domain 0x0 on + chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH + register "c2_latency" = "0x0065" + register "docking_supported" = "0" + register "gen1_dec" = "0x000c0291" # HWM + register "p_cnt_throttling_supported" = "0" + register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" + register "sata_interface_speed_support" = "0x3" + register "sata_port_map" = "0x33" + register "spi_lvscc" = "0x2005" + register "spi_uvscc" = "0x2005" + device pci 16.0 on end # Management Engine Interface 1 + device pci 16.1 off end # Management Engine Interface 2 + device pci 16.2 off end # Management Engine IDE-R + device pci 16.3 off end # Management Engine KT + device pci 19.0 off end # Intel Gigabit Ethernet + device pci 1a.0 on end # USB2 EHCI #2 + device pci 1b.0 on end # High Definition Audio Audio controller + device pci 1c.0 on end # PCIe x1 Port (PCIEX1_1) + device pci 1c.1 on end # PCIe x1 Port (PCIEX1_2) + device pci 1c.2 on end # Realtek RTL8111E Ethernet Controller + device pci 1c.3 on end # ASMedia ASM1042 USB3 Controller + device pci 1c.4 on end # PCIe x1 Port, x16 size (PCIEX16_2) + device pci 1c.5 on end # ASMedia ASM1062 SATA Controller + device pci 1c.6 off end # Unused PCIe Port + device pci 1c.7 off end # Unused PCIe Port + device pci 1d.0 on end # USB2 EHCI #1 + device pci 1e.0 off end # PCI bridge + device pci 1f.0 on # LPC bridge + chip superio/nuvoton/nct6776 + device pnp 2e.0 off end # Floppy + device pnp 2e.1 on # Parallel port + io 0x60 = 0x378 + irq 0x70 = 5 + drq 0x74 = 4 + irq 0xf0 = 0x3c + end + device pnp 2e.2 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 off end # COM2, IR + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + irq 0x72 = 12 + end + device pnp 2e.6 off end # CIR + device pnp 2e.7 off end # GPIO6-9 + device pnp 2e.8 off end # WDT1, GPIO0, GPIO1, GPIOA + device pnp 2e.9 off end # GPIO2-5 + device pnp 2e.a on # ACPI + irq 0xe5 = 0x06 + irq 0xe6 = 0x0c + irq 0xe7 = 0x11 + irq 0xf0 = 0x20 + irq 0xf2 = 0x5d + end + device pnp 2e.b on # HWM, LED + io 0x60 = 0x0290 + io 0x62 = 0x0200 + end + device pnp 2e.d on end # VID + device pnp 2e.e off end # CIR WAKE-UP + device pnp 2e.f on # GPIO Push-Pull or Open-drain + irq 0xf0 = 0x9d + end + device pnp 2e.14 on end # SVID + device pnp 2e.16 on # Deep Sleep + io 0x30 = 0x20 + end + device pnp 2e.17 on # GPIOA + irq 0xe0 = 0xff + irq 0xe1 = 0xff + irq 0xe2 = 0xff + irq 0xe3 = 0xff + irq 0xe5 = 0xff + end + end + end + device pci 1f.2 on end # SATA Controller 1 + device pci 1f.3 on end # SMBus + device pci 1f.5 off end # SATA Controller 2 + device pci 1f.6 off end # Thermal + end + device pci 00.0 on end # Host bridge + device pci 01.0 on end # PCIe bridge for discrete graphics (PCIEX16_1) + device pci 02.0 on end # Internal graphics VGA controller + end +end -- cgit v1.2.3