From 2452afbe04584d48a9d76535f943c0cfc641aa19 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:18:24 +0100 Subject: mb/*/*(ich7/x4x): Use common early southbridge init One functional change is that southbridge GPIO init is moved after console init. Change-Id: I53e6f177aadcdaa8c45593e0a8098e8d3c400d27 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36757 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5qpl-am/romstage.c | 18 +----------------- 1 file changed, 1 insertion(+), 17 deletions(-) (limited to 'src/mainboard/asus/p5qpl-am/romstage.c') diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index 4653b42267..de3972db4e 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -23,7 +23,6 @@ #include #include #include -#include #include #include #include @@ -128,21 +127,6 @@ static int setup_sio_gpio(void) return need_reset; } -static void mb_lpc_setup(void) -{ - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - - ich7_setup_cir(); -} - void mainboard_romstage_entry(void) { // ch0 ch1 @@ -152,13 +136,13 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801gx_lpc_setup(); - mb_lpc_setup(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801gx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); -- cgit v1.2.3