From 3534c1e42de7e534902c3c5bdce30eadb251d081 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sun, 16 Dec 2018 17:17:13 +0100 Subject: mb/asus/p5qpl-am: Add mainboard MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This mainboard has the BSEL straps hooked up to the SuperIO similar to the ASUS P5GC-MX and might therefore require a restart. Tested: - FSB 800, 1067 and 1333MHz CPUs - USB - Ethernet - Serial - 2 DIMM slots - SATA - Libgfxinit (VGA) TESTED with SeaBIOS (sercon disabled) and Linux 4.19. Change-Id: Id845289081751ff8900e366592745f16d96f07c0 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/30250 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asus/p5qpl-am/acpi/ec.asl | 1 + src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl | 47 ++++++++++++++++++++++ src/mainboard/asus/p5qpl-am/acpi/platform.asl | 28 +++++++++++++ src/mainboard/asus/p5qpl-am/acpi/superio.asl | 27 +++++++++++++ 4 files changed, 103 insertions(+) create mode 100644 src/mainboard/asus/p5qpl-am/acpi/ec.asl create mode 100644 src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl create mode 100644 src/mainboard/asus/p5qpl-am/acpi/platform.asl create mode 100644 src/mainboard/asus/p5qpl-am/acpi/superio.asl (limited to 'src/mainboard/asus/p5qpl-am/acpi') diff --git a/src/mainboard/asus/p5qpl-am/acpi/ec.asl b/src/mainboard/asus/p5qpl-am/acpi/ec.asl new file mode 100644 index 0000000000..2997587d82 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/ec.asl @@ -0,0 +1 @@ +/* dummy */ diff --git a/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl new file mode 100644 index 0000000000..ec461679f7 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/ich7_pci_irqs.asl @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This is board specific information: + * IRQ routing for the 0:1e.0 PCI bridge of the ICH7 + */ + +If (PICM) { + Return (Package() { + /* PCI1 SLOT 1 */ + Package() { 0x0000ffff, 0, 0, 0x13}, + Package() { 0x0000ffff, 1, 0, 0x10}, + Package() { 0x0000ffff, 2, 0, 0x11}, + Package() { 0x0000ffff, 3, 0, 0x12}, + + /* PCI1 SLOT 2 */ + Package() { 0x0001ffff, 0, 0, 0x10}, + Package() { 0x0001ffff, 1, 0, 0x11}, + Package() { 0x0001ffff, 2, 0, 0x12}, + Package() { 0x0001ffff, 3, 0, 0x13}, + }) +} Else { + Return (Package() { + Package() { 0x0000ffff, 0, \_SB.PCI0.LPCB.LNKD, 0}, + Package() { 0x0000ffff, 1, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0000ffff, 2, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0000ffff, 3, \_SB.PCI0.LPCB.LNKC, 0}, + + Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0}, + Package() { 0x0001ffff, 1, \_SB.PCI0.LPCB.LNKB, 0}, + Package() { 0x0001ffff, 2, \_SB.PCI0.LPCB.LNKC, 0}, + Package() { 0x0001ffff, 3, \_SB.PCI0.LPCB.LNKD, 0}, + }) +} diff --git a/src/mainboard/asus/p5qpl-am/acpi/platform.asl b/src/mainboard/asus/p5qpl-am/acpi/platform.asl new file mode 100644 index 0000000000..6c92a4ed47 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/platform.asl @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice. */ + Store(Arg0, PICM) +} + +/* SMI I/O Trap */ +Method(TRAP, 1, Serialized) +{ + Store (Arg0, SMIF) /* SMI Function */ + Store (0, TRP0) /* Generate trap */ + Return (SMIF) /* Return value of SMI handler */ +} diff --git a/src/mainboard/asus/p5qpl-am/acpi/superio.asl b/src/mainboard/asus/p5qpl-am/acpi/superio.asl new file mode 100644 index 0000000000..2fc3d8eee8 --- /dev/null +++ b/src/mainboard/asus/p5qpl-am/acpi/superio.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef W83627DHG_SHOW_UARTA +#undef W83627DHG_SHOW_UARTB +#undef W83627DHG_SHOW_KBC +#undef W83627DHG_SHOW_PS2M +#undef W83627DHG_SHOW_HWMON +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define W83627DHG_SHOW_UARTA +#define W83627DHG_SHOW_KBC +#define W83627DHG_SHOW_PS2M +#define W83627DHG_SHOW_HWMON +#include -- cgit v1.2.3