From 2d69d594de86077e4d98b7ffbc29b24e547faaa9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 1 Jan 2020 19:32:06 +0100 Subject: mb/asus/p5ql-em/devicetree.cb: Do minor fixes Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode. Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/asus/p5ql-em/devicetree.cb | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'src/mainboard/asus/p5ql-em') diff --git a/src/mainboard/asus/p5ql-em/devicetree.cb b/src/mainboard/asus/p5ql-em/devicetree.cb index fd0b1034af..ab9860b16a 100644 --- a/src/mainboard/asus/p5ql-em/devicetree.cb +++ b/src/mainboard/asus/p5ql-em/devicetree.cb @@ -18,7 +18,7 @@ chip northbridge/intel/x4x # Northbridge device lapic 0 on end end chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end + device lapic 0xacac off end end end device domain 0 on # PCI domain @@ -41,10 +41,7 @@ chip northbridge/intel/x4x # Northbridge chip southbridge/intel/i82801jx # Southbridge register "gpe0_en" = "0x40" - # Set AHCI mode. register "sata_port_map" = "0x3f" - register "sata_clock_request" = "0" - register "sata_traffic_monitor" = "0" # Enable PCIe ports 0,1,3,4,5 as slots. register "pcie_slot_implemented" = "0x3b" -- cgit v1.2.3