From aa990e928910e35edb115095898c4668becdf1d8 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 11 Nov 2019 20:08:12 +0100 Subject: sb/intel/i82801jx: Move early sb init to a common place Setting southbridge GPIO is now done after console init, which should be fine. This code is partially copied from i82801ix. Change-Id: I51dd30de4a82898b0f1d8c4308e8de4a00d1b7aa Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36756 Reviewed-by: Angel Pons Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- src/mainboard/asus/p5qc/romstage.c | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) (limited to 'src/mainboard/asus/p5qc') diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 3462a3d99d..9a90f74189 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -17,7 +17,6 @@ #include #include #include -#include #include #include #include @@ -31,20 +30,8 @@ * We should use standard gpio.h eventually */ -static void mb_gpio_init(void) +static void mb_misc_rcba(void) { - /* Set the value for GPIO base address register and enable GPIO. */ - pci_write_config32(LPC_DEV, D31F0_GPIO_BASE, (DEFAULT_GPIOBASE | 1)); - pci_write_config8(LPC_DEV, D31F0_GPIO_CNTL, 0x10); - - setup_pch_gpios(&mainboard_gpio_map); - - /* Set default GPIOs on superio: TODO (here or in ramstage) */ - - /* Enable IOAPIC */ - RCBA8(0x31ff) = 0x03; - RCBA8(0x31ff); - /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; @@ -59,13 +46,14 @@ void mainboard_romstage_entry(void) /* Set southbridge and Super I/O GPIOs. */ i82801jx_lpc_setup(); - mb_gpio_init(); + mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); enable_smbus(); + i82801jx_early_init(); x4x_early_init(); s3_resume = southbridge_detect_s3_resume(); -- cgit v1.2.3