From d2f3afcc17df44589bd1f8b09e5c3a33edf64982 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 1 Jan 2020 19:19:47 +0100 Subject: mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixes Use lowercase for hex constants and align some comments. Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber --- src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/asus/p5qc/variants/p5ql_pro') diff --git a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb index 0428b50e9a..4e27b467d9 100644 --- a/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb +++ b/src/mainboard/asus/p5qc/variants/p5ql_pro/devicetree.cb @@ -20,8 +20,8 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end + chip cpu/intel/model_1067x # CPU + device lapic 0xacac off end end end device domain 0 on # PCI domain @@ -43,7 +43,7 @@ chip northbridge/intel/x4x # Northbridge register "sata_traffic_monitor" = "0" # Enable PCIe ports 0,2,3 as slots. - register "pcie_slot_implemented" = "0x31" + register "pcie_slot_implemented" = "0x31" register "gen1_dec" = "0x00000295" register "gen2_dec" = "0x001c4701" -- cgit v1.2.3