From 08311f5033e3adccb8794b6113d72bf7a76e4d00 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 19 Apr 2016 07:17:59 +0300 Subject: AGESA vendorcode: Build a common amdlib MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Having CFLAGS with -Os disables -falign-function, for unlucky builds this may delay entry to ramstage by 600ms. Build the low-level IO functions aligned with -O2 instead. Change-Id: Ice6781666a0834f1e8e60a0c93048ac8472f27d9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/14414 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/asus/m5a88-v/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/asus/m5a88-v') diff --git a/src/mainboard/asus/m5a88-v/Makefile.inc b/src/mainboard/asus/m5a88-v/Makefile.inc index 45c257ad24..7b6a8e6ce5 100644 --- a/src/mainboard/asus/m5a88-v/Makefile.inc +++ b/src/mainboard/asus/m5a88-v/Makefile.inc @@ -2,8 +2,8 @@ #SB800 CIMx share AGESA V5 lib code ifneq ($(CONFIG_CPU_AMD_AGESA),y) AGESA_ROOT ?= src/vendorcode/amd/agesa/f14 - romstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c - ramstage-y += ../../../../$(AGESA_ROOT)/Lib/amdlib.c + romstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c + ramstage-y += ../../../../$(AGESA_ROOT)/../common/amdlib.c AGESA_INC := -I$(AGESA_ROOT)/ \ -I$(AGESA_ROOT)/../common \ -- cgit v1.2.3