From 1740230ace3aeede3a7ee5cadd1e17744cda07b3 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 24 May 2018 00:04:22 +0300 Subject: Remove all AMD K8 boards MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Platforms with LATE_CBMEM_INIT were agreed to be removed with 4.7 release late 2017. Change-Id: I0ecbb40f8c7ebdf68217f50af5624905d9005c64 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26671 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/asus/m2n-e/mptable.c | 102 ------------------------------------- 1 file changed, 102 deletions(-) delete mode 100644 src/mainboard/asus/m2n-e/mptable.c (limited to 'src/mainboard/asus/m2n-e/mptable.c') diff --git a/src/mainboard/asus/m2n-e/mptable.c b/src/mainboard/asus/m2n-e/mptable.c deleted file mode 100644 index 5d9f0fc400..0000000000 --- a/src/mainboard/asus/m2n-e/mptable.c +++ /dev/null @@ -1,102 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 Uwe Hermann - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include -#include -#include -#include -#include -#include - -#define PCI_INT(bus, dev, fn, pin) \ - smp_write_intsrc(mc, mp_INT, \ - MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_LOW, \ - bus_mcp55[bus], (((dev) << 2) | (fn)), apicid_mcp55, (pin)) - -extern unsigned char bus_mcp55[8]; -extern unsigned apicid_mcp55; - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - unsigned int sbdn; - int i, j, bus_isa; - struct device *dev; - struct resource *res; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - get_bus_conf(); - sbdn = sysconf.sbdn; - - mptable_write_buses(mc, NULL, &bus_isa); - - dev = dev_find_slot(bus_mcp55[0], PCI_DEVFN(sbdn + 0x1, 0)); - if (dev) { - res = find_resource(dev, PCI_BASE_ADDRESS_1); - if (res) - smp_write_ioapic(mc, apicid_mcp55, 0x11, - res2mmio(res, 0, 0)); - - pci_write_config32(dev, 0x7c, 0x00000000); - pci_write_config32(dev, 0x80, 0x11002009); - pci_write_config32(dev, 0x84, 0x2000dd08); - } - - mptable_add_isa_interrupts(mc, bus_isa, apicid_mcp55, 0); - - /* I/O Ints */ - PCI_INT(0, sbdn + 1, 1, 10); /* SMBus */ - PCI_INT(0, sbdn + 2, 0, 20); /* USB 1.1 */ - PCI_INT(0, sbdn + 2, 1, 22); /* USB 2.0 */ - PCI_INT(0, sbdn + 4, 0, 14); /* IDE */ - PCI_INT(0, sbdn + 5, 0, 23); /* SATA 0 */ - PCI_INT(0, sbdn + 5, 1, 23); /* SATA 1 */ - PCI_INT(0, sbdn + 5, 2, 22); /* SATA 2 */ - PCI_INT(0, sbdn + 6, 1, 21); /* HD audio */ - PCI_INT(0, sbdn + 8, 0, 24); /* NIC */ - - /* PCI-E slots (two x1, one x4, one x16) */ - for (j = 7; j >= 2; j--) { - if (!bus_mcp55[j]) - continue; - for (i = 0; i < 4; i++) - PCI_INT(j, 0, i, 0x10 + (2 + j + i + 4 - sbdn % 4) % 4); - } - - /* PCI slots (three on this board) */ - for (j = 0; j < 3; j++) { - for (i = 0; i < 4; i++) - PCI_INT(1, 0x06 + j, i, 0x10 + (2 + i + j) % 4); - } - - /* Local Ints: Type Trigger Polarity Bus ID IRQ APIC ID PIN# */ - mptable_lintsrc(mc, bus_isa); - - /* Compute the checksums. */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} -- cgit v1.2.3