From 3dce9f09d9e26b147153ad0cda493ecb4b6d15d8 Mon Sep 17 00:00:00 2001 From: Gergely Kiss Date: Wed, 27 Dec 2017 15:24:04 +0100 Subject: mainboard/asus/am1i-a: add support for board ASUS AM1I-A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add code to support the board ASUS AM1I-A. Tested with multiple payloads and OSes with satisfactory results. S3 suspend/resume works fine with Linux but has issues with Windows (an exception is thrown). However, after manually rebooting, Windows resumes the suspended session. * Tested with: SeaBIOS 1.11 + Linux 4.10 - OK * Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK * Tested with: FILO 0.6.0 - hangs after showing the banner Details are going to be published on the board's status page. Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7 Signed-off-by: Gergely Kiss Reviewed-on: https://review.coreboot.org/23002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asus/am1i-a/dsdt.asl | 80 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 80 insertions(+) create mode 100644 src/mainboard/asus/am1i-a/dsdt.asl (limited to 'src/mainboard/asus/am1i-a/dsdt.asl') diff --git a/src/mainboard/asus/am1i-a/dsdt.asl b/src/mainboard/asus/am1i-a/dsdt.asl new file mode 100644 index 0000000000..4d91b2a16c --- /dev/null +++ b/src/mainboard/asus/am1i-a/dsdt.asl @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2015 Sergej Ivanov + * Copyright (C) 2018 Gergely Kiss + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "AMD ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include */ /* Include global debug methods if needed */ + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Contains the supported sleep states for this chipset */ + #include + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + #include "acpi/routing.asl" + + Device(PWRB) { + Name(_HID, EISAID("PNP0C0C")) + Name(_UID, 0xAA) + Name(_PRW, Package () {3, 0x04}) + Name(_STA, 0x0B) + } + + Device(PCI0) { + /* Describe the AMD Northbridge */ + #include + + /* Describe the AMD Fusion Controller Hub Southbridge */ + #include + } + + /* Describe PCI INT[A-H] for the Southbridge */ + #include + + } /* End \_SB scope */ + + /* Describe SMBUS for the Southbridge */ + #include + + /* Define the System Indicators for the platform */ + #include "acpi/si.asl" +} +/* End of ASL file */ -- cgit v1.2.3