From 3dce9f09d9e26b147153ad0cda493ecb4b6d15d8 Mon Sep 17 00:00:00 2001 From: Gergely Kiss Date: Wed, 27 Dec 2017 15:24:04 +0100 Subject: mainboard/asus/am1i-a: add support for board ASUS AM1I-A MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add code to support the board ASUS AM1I-A. Tested with multiple payloads and OSes with satisfactory results. S3 suspend/resume works fine with Linux but has issues with Windows (an exception is thrown). However, after manually rebooting, Windows resumes the suspended session. * Tested with: SeaBIOS 1.11 + Linux 4.10 - OK * Tested with: tianocore vEDK2017 + MS Windows 8.1 - OK * Tested with: FILO 0.6.0 - hangs after showing the banner Details are going to be published on the board's status page. Change-Id: I3d9432849560df81536bbb2ce4c87cd265b820f7 Signed-off-by: Gergely Kiss Reviewed-on: https://review.coreboot.org/23002 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asus/am1i-a/devicetree.cb | 105 ++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) create mode 100644 src/mainboard/asus/am1i-a/devicetree.cb (limited to 'src/mainboard/asus/am1i-a/devicetree.cb') diff --git a/src/mainboard/asus/am1i-a/devicetree.cb b/src/mainboard/asus/am1i-a/devicetree.cb new file mode 100644 index 0000000000..b81048708a --- /dev/null +++ b/src/mainboard/asus/am1i-a/devicetree.cb @@ -0,0 +1,105 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2013 Advanced Micro Devices, Inc. +# Copyright (C) 2015 Sergej Ivanov +# Copyright (C) 2018 Gergely Kiss +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/agesa/family16kb/root_complex + device cpu_cluster 0 on + chip cpu/amd/agesa/family16kb + device lapic 0 on end + end + end + + device domain 0 on + subsystemid 0x1043 0x8623 inherit + chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + chip northbridge/amd/agesa/family16kb # PCI side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x9804 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 off end # GPP Bridge 1 - not used + device pci 2.3 off end # GPP Bridge 2 - not used + device pci 2.4 off end # GPP Bridge 3 - not used + device pci 2.5 on end # Realtek GBE + end #chip northbridge/amd/agesa/family16kb + + chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SM + chip drivers/generic/generic #dimm 0-0-0 + device i2c 50 on end + end + chip drivers/generic/generic #dimm 0-0-1 + device i2c 51 on end + end + end # SM + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8623e + device pnp 2e.0 off end # FDC - not used + device pnp 2e.1 on # COM1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 on # COM2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 on # Parallel port + io 0x60 = 0x378 + io 0x62 = 0x778 # for ECP mode + irq 0x70 = 5 + drq 0x74 = 3 + end + device pnp 2e.4 on # EC + io 0x60 = 0x290 + io 0x62 = 0x230 + end + device pnp 2e.5 on # PS/2 keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 on # PS/2 mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x62 = 0x300 + end + end #superio/ite/it8623e + end #device pci 14.3 # LPC + device pci 14.7 off end # SD - no card reader present + end #chip southbridge/amd/agesa/hudson + + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + register "spdAddrLookup" = " + { + { {0xA0, 0xA2} }, + }" + + end #chip northbridge/amd/agesa/family16kb # CPU side of HT root complex + end #domain +end #northbridge/amd/agesa/family16kb/root_complex -- cgit v1.2.3