From 42fa7fe28b60b448f501e99ee285a0af12c86d34 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Wed, 20 Apr 2011 20:54:07 +0000 Subject: run uart_init() from console_init, just like the other console initialization functions. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asus/a8v-e_deluxe/romstage.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mainboard/asus/a8v-e_deluxe') diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 6785a2fca2..47a0e656f1 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -159,11 +159,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); enable_rom_decode(); - print_info("now booting... fallback\n"); + print_info("now booting... romstage\n"); /* Is this a CPU only reset? Or is this a secondary CPU? */ if (!cpu_init_detectedx && boot_cpu()) { @@ -174,7 +173,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) sio_init(); w83627ehg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - uart_init(); console_init(); enable_rom_decode(); -- cgit v1.2.3