From d3f01b21fa7bf9bf115088ddc032aa1cd0000945 Mon Sep 17 00:00:00 2001 From: Tristan Corrick Date: Thu, 6 Dec 2018 22:46:58 +1300 Subject: sb/intel/lynxpoint: Handle H81 only having 6 PCIe root ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The H81 chipset is the only non-LP Lynx Point chipset with 6 PCIe root ports, all others have 8 [1]. The existing PCIe code assumed that all non-LP chipsets had 8 root ports, which meant that port 6 would not be considered the last root port on H81, so `root_port_commit_config()` would not run. Ultimately, while PCIe still worked on H81, all the root ports would remain enabled, even if disabled in the devicetree. Also, remove `PCI_DEVICE_ID_INTEL_LYNXPOINT_MOB_DESK_{MIN,MAX}`, as they are unused, and the MAX constant is incorrect. Interestingly, this fixes an issue where GRUB is unable to halt the system. Tested on an ASRock H81M-HDS. The root ports disabled in the devicetree do indeed end up disabled. [1] Intel® 8 Series/C220 Series Chipset Family Platform Controller Hub (PCH) Datasheet, revision 003, document number 328904. Change-Id: If3ce217e8a4f4ea4e111e4525b03dbbfc63f92b0 Signed-off-by: Tristan Corrick Reviewed-on: https://review.coreboot.org/c/30077 Reviewed-by: Arthur Heymans Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/asrock/h81m-hds/devicetree.cb | 2 -- 1 file changed, 2 deletions(-) (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/h81m-hds/devicetree.cb b/src/mainboard/asrock/h81m-hds/devicetree.cb index 32b5978092..58a319d086 100644 --- a/src/mainboard/asrock/h81m-hds/devicetree.cb +++ b/src/mainboard/asrock/h81m-hds/devicetree.cb @@ -102,8 +102,6 @@ chip northbridge/intel/haswell device pci 1c.5 on # PCIe 1x slot subsystemid 0x1849 0x8c1a end - device pci 1c.6 off end # PCIe port #7 - device pci 1c.7 off end # PCIe port #8 device pci 1d.0 on # EHCI controller #1 subsystemid 0x1849 0x8c26 end -- cgit v1.2.3