From d1cb0eecd130cb4259ce9fedb32ebcd9ada0d4b7 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 4 Jun 2011 10:37:35 -0700 Subject: sb800: move spi prefetch and fast read mode to sb bootblock. So we don't waste time on the first cbfs scan. Signed-off-by: Stefan Reinauer Signed-off-by: Patrick Georgi [adapt persimmon with the same change, and work around romcc bug in bootblock code: it doesn't like MEMACCESS[idx] |= value;] Change-Id: Ic4d0e53d3102be0de0bd18b1b8b29c500bd6d997 Reviewed-on: http://review.coreboot.org/9 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Marc Jones --- src/mainboard/asrock/e350m1/romstage.c | 17 ----------------- 1 file changed, 17 deletions(-) (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/e350m1/romstage.c b/src/mainboard/asrock/e350m1/romstage.c index 7d25ec1d38..61de9f6ee8 100644 --- a/src/mainboard/asrock/e350m1/romstage.c +++ b/src/mainboard/asrock/e350m1/romstage.c @@ -55,23 +55,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time __writemsr(0xc0010062, 0); - // early enable of PrefetchEnSPIFromHost - if (boot_cpu()) { - __outdword(0xcf8, 0x8000a3b8); - __outdword(0xcfc, __indword(0xcfc) | 1 << 24); - } - // early enable of SPI 33 MHz fast mode read - if (boot_cpu()) { - volatile u32 *spiBase = (void *)0xa0000000; - u32 save; - __outdword(0xcf8, 0x8000a3a0); - save = __indword(0xcfc); - __outdword(0xcfc, (u32) spiBase | 2); // set temp MMIO base - spiBase[3] = (spiBase[3] & ~(3 << 14)) | (1 << 14); - spiBase[0] |= 1 << 18; // fast read enable - __outdword(0xcfc, save); // clear temp base - } - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); sb_poweron_init(); -- cgit v1.2.3