From b9d2589ca40026b543ecb5b008ce0d1bc346bf53 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 15 Jun 2018 22:02:28 +0200 Subject: mb/*/*: Harmonise FD and devicetree on boards featuring ICH7 On some boards the devicetree and Function Disable register did not match. In this case the FD values are put in the devicetree as these were the values that were actually used in practice. A complete devicetree will make it easier to automatically disable devices in ramstage. Change-Id: I1692ca5f490ea84e2fc520d3f66044ad7514f76e Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/27122 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb | 3 --- src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 3 --- 2 files changed, 6 deletions(-) (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index dba3a69cb1..833ea00ad7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -151,9 +151,6 @@ chip northbridge/intel/x4x # Northbridge device i2c 69 on end end end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end end end end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index d4708c6059..63bcbc8d39 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -131,9 +131,6 @@ chip northbridge/intel/x4x # Northbridge device pci 1f.3 on # SMbus subsystemid 0x1849 0x27da end - device pci 1f.4 off end - device pci 1f.5 off end - device pci 1f.6 off end end end end -- cgit v1.2.3