From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asrock/939a785gmh/romstage.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index da0f9ac92d..7fb3227661 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -21,9 +21,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include @@ -40,6 +37,7 @@ #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" #include "lib/delay.c" +#include #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" -- cgit v1.2.3