From 837403dddf7b05b1a2b1a09a2cd57975484c7568 Mon Sep 17 00:00:00 2001 From: Rudolf Marek Date: Sat, 26 Feb 2011 19:46:08 +0000 Subject: Following patch fills in the callbacks for PCIe x16 resets. This board uses GPM8,GPM9 as reset toggles. Signed-off-by: Rudolf Marek Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/asrock/939a785gmh/mainboard.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) (limited to 'src/mainboard/asrock') diff --git a/src/mainboard/asrock/939a785gmh/mainboard.c b/src/mainboard/asrock/939a785gmh/mainboard.c index 09ace66fca..c7eedeafb8 100644 --- a/src/mainboard/asrock/939a785gmh/mainboard.c +++ b/src/mainboard/asrock/939a785gmh/mainboard.c @@ -35,12 +35,31 @@ uint64_t uma_memory_base, uma_memory_size; void set_pcie_dereset(void); void set_pcie_reset(void); u8 is_dev3_present(void); + +static void pcie_rst_toggle(u8 val) { + u8 byte; + + byte = pm_ioread(0x8d); + byte &= ~(3 << 1); + pm_iowrite(0x8d, byte); + + byte = pm_ioread(0x94); + /* Output enable */ + byte &= ~(3 << 2); + /* Toggle GPM8, GPM9 */ + byte &= ~(3 << 0); + byte |= val; + pm_iowrite(0x94, byte); +} + void set_pcie_dereset() { + pcie_rst_toggle(0x3); } void set_pcie_reset() { + pcie_rst_toggle(0x0); } #if 0 /* not tested yet */ -- cgit v1.2.3