From 90857b7381d6fcccc9a03757f2b22de64baf0785 Mon Sep 17 00:00:00 2001
From: Nicholas Chin <nic.c3.14@gmail.com>
Date: Tue, 13 Feb 2024 21:16:24 +0100
Subject: mb/asrock: Add Z87E-ITX (Haswell)

This was done using Haswell autoport, with manual fixes to get the
output to build against current main. I do not physically have this
board; I was sent the output of autoport with some fixes on top of
which I added additional changes. The VBT was copied from
/sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware.

The flash chip is 8MiB in a socketed DIP8 package, making it easy to
externally flash to recover from a brick.

Working:
- Haswell MRC.bin
- S3 suspend and resume
- Libgfxinit
- HDMI
- DVI-I (including passive DVI to VGA adapter)
- DisplayPort
- SATA ports
- mSATA SSD
- mPCIe WiFi slot
- Rear USB ports
- USB 3.0 header
- Audio header
- Ethernet
- x16 PCIe slot
- EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector)
- edk2 (MrChromebox uefipayload_202309)

Not Tested:
- PS/2 keyboard/mouse
- eSATA
- USB 2.0 header

Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/asrock/z87e-itx/dsdt.asl | 27 +++++++++++++++++++++++++++
 1 file changed, 27 insertions(+)
 create mode 100644 src/mainboard/asrock/z87e-itx/dsdt.asl

(limited to 'src/mainboard/asrock/z87e-itx/dsdt.asl')

diff --git a/src/mainboard/asrock/z87e-itx/dsdt.asl b/src/mainboard/asrock/z87e-itx/dsdt.asl
new file mode 100644
index 0000000000..b62c922dc2
--- /dev/null
+++ b/src/mainboard/asrock/z87e-itx/dsdt.asl
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <acpi/acpi.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018	/* OEM revision */
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	/* global NVS and variables. */
+	#include <southbridge/intel/lynxpoint/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0)
+	{
+		#include <northbridge/intel/haswell/acpi/hostbridge.asl>
+		#include <southbridge/intel/lynxpoint/acpi/pch.asl>
+	}
+}
-- 
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