From a0d9ad322fe603d4d4cbccda9c7edcfbf0b13409 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 3 Jan 2022 18:07:13 +0000 Subject: soc/intel/skl: Replace dt `HeciEnabled` by `HECI1 disable` config List of changes: 1. Drop `HeciEnabled` from dt and dt chip configuration. 2. Replace all logic that disables HECI1 based on the `HeciEnabled` chip config with `DISABLE_HECI1_AT_PRE_BOOT` config. 3. Make dt CSE PCI device `on` by default. 4. Mainboards set DISABLE_HECI1_AT_PRE_BOOT=y to make Heci1 function disable at pre-boot instead of the dt policy that uses `HeciEnabled = 0`. Mainboards that choose to make HECI1 enable during boot don't override `heci1 disable` config. Signed-off-by: Subrata Banik Change-Id: I5c13fe4a78be44403a81c28b1676aecc26c58607 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60722 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/asrock/h110m/Kconfig | 3 +++ src/mainboard/asrock/h110m/devicetree.cb | 3 --- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/asrock/h110m') diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index 3a55f9e1f3..7f84adb5b7 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -17,6 +17,9 @@ config BOARD_SPECIFIC_OPTIONS select RT8168_SET_LED_MODE select MAINBOARD_HAS_LPC_TPM +config DISABLE_HECI1_AT_PRE_BOOT + default y + config MAINBOARD_DIR default "asrock/h110m" diff --git a/src/mainboard/asrock/h110m/devicetree.cb b/src/mainboard/asrock/h110m/devicetree.cb index aed9184e99..a45127c0b3 100644 --- a/src/mainboard/asrock/h110m/devicetree.cb +++ b/src/mainboard/asrock/h110m/devicetree.cb @@ -101,9 +101,6 @@ chip soc/intel/skylake device pci 15.3 off end # I2C #3 device pci 16.0 on # Management Engine Interface 1 subsystemid 0x1849 0xa131 - - # FIXME: does not match devicetree! - register "HeciEnabled" = "0" end device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R -- cgit v1.2.3