From 157b189f6b97b6e9ecd8d29edbbd045fbbc231f5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Fri, 16 Aug 2019 14:02:25 +0300 Subject: cpu/intel: Enter romstage without BIST MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/asrock/g41c-gs/romstage.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/mainboard/asrock/g41c-gs') diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index de73d016d3..7a2004f141 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include @@ -82,7 +81,7 @@ static void ich7_enable_lpc(void) pci_write_config32(PCI_DEV(0, 0x1f, 0), GEN1_DEC, 0x000c0291); } -void mainboard_romstage_entry(unsigned long bist) +void mainboard_romstage_entry(void) { // ch0 ch1 const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; @@ -95,7 +94,6 @@ void mainboard_romstage_entry(unsigned long bist) console_init(); - report_bist_failure(bist); enable_smbus(); x4x_early_init(); -- cgit v1.2.3