From fecf77770b8e68b9ef82021ca53c31db93736d93 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Sat, 9 Nov 2019 14:19:04 +0100 Subject: sb/intel/i82801gx: Add common LPC decode code Generic LPC decode ranges can now be set from the devicetree. Change-Id: I1065ec770ad3a743286859efa39dca09ccb733a1 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/36700 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes Reviewed-by: Nico Huber Reviewed-by: Angel Pons --- src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb | 2 ++ src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb | 2 ++ src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 2 ++ src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb | 2 ++ src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb | 2 ++ 5 files changed, 10 insertions(+) (limited to 'src/mainboard/asrock/g41c-gs/variants') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index acb8ac6702..b68aaa9fa7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -54,6 +54,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb index 805f2dac93..160d025ca7 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs/devicetree.cb @@ -48,6 +48,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index f4d1dc4291..0a8f27546d 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -49,6 +49,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb index 2fd6e4f649..8119ced94c 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-s3/devicetree.cb @@ -47,6 +47,8 @@ chip northbridge/intel/x4x # Northbridge register "sata_ports_implemented" = "0x3" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 5479faf3e9..e5e3cf9b90 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -48,6 +48,8 @@ chip northbridge/intel/x4x # Northbridge register "ide_enable_primary" = "0x1" register "gpe0_en" = "0x440" + register "gen1_dec" = "0x000c0291" # Superio HWM + device pci 1b.0 on # Audio subsystemid 0x1849 0x3662 end -- cgit v1.2.3