From 98c92570d9bb363740ae1b2cbbefc3c0f2404cb4 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 11:39:58 +0100 Subject: cpu/intel/speedstep: Have nb and sb code provide c5/c6/slfm C5, C6 and slfm depend on the southbridge and the northbridge to be able to provide this functionality, with some just lacking the possibility to do so. Move the devicetree configuration to the southbridge. This removes the need for a magic lapic in the devicetree. Change-Id: I4a9b1e684a7927259adae9b1d42a67e907722109 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69297 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Angel Pons --- src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb | 3 --- 1 file changed, 3 deletions(-) (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb index 23268f2bdf..0dbe8d9685 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-vs3-r2/devicetree.cb @@ -6,9 +6,6 @@ chip northbridge/intel/x4x # Northbridge chip cpu/intel/socket_LGA775 device lapic 0 on end end - chip cpu/intel/model_1067x # CPU - device lapic 0xACAC off end - end end device domain 0 on ops x4x_pci_domain_ops # PCI domain -- cgit v1.2.3