From 1eecb8c814fa05e9902ddcb139a6e8b3a226ffa6 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 10:04:56 +0100 Subject: nb/intel/x4x: Hook up PCI domain and CPU bus ops to devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I0a7b3167392c152da6459dfc202ef11b2e61400a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69295 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/mainboard/asrock/g41c-gs/variants/g41m-gs') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb index c3c6b1b17a..818ceaa5c0 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41m-gs/devicetree.cb @@ -1,7 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on # APIC cluster + device cpu_cluster 0 on + ops x4x_cpu_bus_ops # APIC cluster chip cpu/intel/socket_LGA775 device lapic 0 on end end @@ -9,7 +10,8 @@ chip northbridge/intel/x4x # Northbridge device lapic 0xACAC off end end end - device domain 0 on # PCI domain + device domain 0 on + ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit device pci 0.0 on # Host Bridge subsystemid 0x1849 0x2e30 -- cgit v1.2.3