From 803029685f96bccac13359fc616d1577508ba764 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Mon, 7 Nov 2022 11:49:22 +0100 Subject: nb/intel/x4x: Remove apic 0 from devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This is added at runtime. Change-Id: I7716f8a972e2280179aa6aee00488b22413c0c73 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/69298 Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb | 7 +------ 1 file changed, 1 insertion(+), 6 deletions(-) (limited to 'src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2') diff --git a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb index 28b24d8742..3eeeafd4a6 100644 --- a/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb +++ b/src/mainboard/asrock/g41c-gs/variants/g41c-gs-r2/devicetree.cb @@ -1,12 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-or-later chip northbridge/intel/x4x # Northbridge - device cpu_cluster 0 on - ops x4x_cpu_bus_ops # APIC cluster - chip cpu/intel/socket_LGA775 - device lapic 0 on end - end - end + device cpu_cluster 0 on ops x4x_cpu_bus_ops end # APIC cluster device domain 0 on ops x4x_pci_domain_ops # PCI domain subsystemid 0x1458 0x5000 inherit -- cgit v1.2.3