From af258cc1791b5c46fcb13d41128cc99043a435be Mon Sep 17 00:00:00 2001 From: Michał Żygowski Date: Sun, 1 Dec 2019 17:42:04 +0100 Subject: mb/*/*: use ACPIMMIO common block wherever possible MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TEST=boot PC Engines apu2 and launch Debian Linux Signed-off-by: Michał Żygowski Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/asrock/e350m1/BiosCallOuts.c | 148 ++++++++++++++--------------- 1 file changed, 71 insertions(+), 77 deletions(-) (limited to 'src/mainboard/asrock/e350m1/BiosCallOuts.c') diff --git a/src/mainboard/asrock/e350m1/BiosCallOuts.c b/src/mainboard/asrock/e350m1/BiosCallOuts.c index 5d7211c3e6..c9ecad746a 100644 --- a/src/mainboard/asrock/e350m1/BiosCallOuts.c +++ b/src/mainboard/asrock/e350m1/BiosCallOuts.c @@ -15,6 +15,7 @@ #include #include +#include #include #include @@ -34,88 +35,81 @@ const BIOS_CALLOUT_STRUCT BiosCallouts[] = }; const int BiosCalloutsLen = ARRAY_SIZE(BiosCallouts); -/* Call the host environment interface to provide a user hook opportunity. */ +/* Call the host environment interface to provide a user hook opportunity. */ static AGESA_STATUS board_BeforeDramInit (UINT32 Func, UINTN Data, VOID *ConfigPtr) { - AGESA_STATUS Status; - UINTN FcnData; - MEM_DATA_STRUCT *MemData; - UINT32 AcpiMmioAddr; - UINT32 GpioMmioAddr; - UINT8 Data8; - UINT16 Data16; - UINT8 TempData8; + AGESA_STATUS Status; + UINTN FcnData; + MEM_DATA_STRUCT *MemData; + UINT32 AcpiMmioAddr; + UINT32 GpioMmioAddr; + UINT8 Data8; + UINT8 TempData8; - FcnData = Data; - MemData = ConfigPtr; + FcnData = Data; + MemData = ConfigPtr; - Status = AGESA_SUCCESS; - /* Get SB800 MMIO Base (AcpiMmioAddr) */ - WriteIo8 (0xCD6, 0x27); - Data8 = ReadIo8(0xCD7); - Data16 = Data8 << 8; - WriteIo8 (0xCD6, 0x26); - Data8 = ReadIo8(0xCD7); - Data16 |= Data8; - AcpiMmioAddr = (UINT32)Data16 << 16; - GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; + Status = AGESA_SUCCESS; + AcpiMmioAddr = AMD_SB_ACPI_MMIO_ADDR; + GpioMmioAddr = AcpiMmioAddr + GPIO_BASE; - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~BIT5; + TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); - Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~BIT5; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x03; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - Data8 |= BIT2+BIT3; - Data8 &= ~BIT4; - TempData8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - TempData8 &= 0x23; - TempData8 |= Data8; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, TempData8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~BIT5; + TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x03; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); + Data8 |= BIT2+BIT3; + Data8 &= ~BIT4; + TempData8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + TempData8 &= 0x23; + TempData8 |= Data8; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, TempData8); - /* this seems to be just copy-pasted from the AMD reference boards and needs - * some investigation - */ - switch(MemData->ParameterListPtr->DDR3Voltage){ - case VOLT1_35: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_25: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - break; - case VOLT1_5: - default: - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG178); - Data8 |= (UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); - Data8 = Read64Mem8 (GpioMmioAddr+SB_GPIO_REG179); - Data8 &= ~(UINT8)BIT6; - Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); - } - // disable memory clear for boot time reduction - MemData->ParameterListPtr->EnableMemClr = FALSE; - return Status; + /* + * this seems to be just copy-pasted from the AMD reference boards and + * needs some investigation + */ + switch (MemData->ParameterListPtr->DDR3Voltage) { + case VOLT1_35: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_25: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + break; + case VOLT1_5: + default: + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG178); + Data8 |= (UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG178, Data8); + Data8 = Read64Mem8(GpioMmioAddr+SB_GPIO_REG179); + Data8 &= ~(UINT8)BIT6; + Write64Mem8(GpioMmioAddr+SB_GPIO_REG179, Data8); + } + /* disable memory clear for boot time reduction */ + MemData->ParameterListPtr->EnableMemClr = FALSE; + return Status; } -- cgit v1.2.3