From 5f23b6cd7d97a25aecaa29adb5dcb39afa296af6 Mon Sep 17 00:00:00 2001 From: "Ronald G. Minnich" Date: Tue, 19 Sep 2006 17:37:32 +0000 Subject: add the msm800srv ; put the usb in the right place. git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2426 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/artecgroup/dbe61/cs5536_usb.c | 95 ----------------------------- 1 file changed, 95 deletions(-) delete mode 100644 src/mainboard/artecgroup/dbe61/cs5536_usb.c (limited to 'src/mainboard/artecgroup') diff --git a/src/mainboard/artecgroup/dbe61/cs5536_usb.c b/src/mainboard/artecgroup/dbe61/cs5536_usb.c deleted file mode 100644 index b7fecbfcf3..0000000000 --- a/src/mainboard/artecgroup/dbe61/cs5536_usb.c +++ /dev/null @@ -1,95 +0,0 @@ -#include -#include -#include -#include -#include - -#include -#include - -#include "cs5536.h" - -#define GLIU2_P2D_BM_1 0x51010021 // southbridge GLIU P2D base mask descriptor -#define USBMSRUOCB 0x5120000b // USB option controller base address register -#define UOCMUX (USBOC_BASE_ADDRESS + 4) // option controller native multiplex register - -#define USBOC_BASE_ADDRESS 0xe1017000 // USB option contoller base address, used only here -#define USBOC_PORT4_FUNCTION 2 // USB port 4 desired function (0 = disabled, 2 = host, 3 = device) - -static void ohci_init(struct device *dev) -{ - uint32_t n; - msr_t msr; - - printk_debug("USB: Setting up OHCI controller... "); - - // enable controller bus mastering - n = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - n | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - // set the USB option controller base address - msr.hi = 0x0000000a; - msr.lo = USBOC_BASE_ADDRESS; - wrmsr(USBMSRUOCB, msr); - - // create the GLIU memory mapping - msr.hi = 0x40000000 | ((USBOC_BASE_ADDRESS >> 24) & 0x000000ff); - msr.lo = ((USBOC_BASE_ADDRESS << 8) & 0xfff00000) | 0x000fffff; - wrmsr(GLIU2_P2D_BM_1, msr); - - // set the multiplex register with port 4 function - *((uint32_t*)UOCMUX) = USBOC_PORT4_FUNCTION; - - // finally, disable the USB option controller memory mapping - msr.hi = 0x000000ff; - msr.lo = 0xfff00000; - wrmsr(GLIU2_P2D_BM_1, msr); - - printk_debug("done.\n"); -} - -static void ehci_init(struct device *dev) -{ - uint32_t cmd; - printk_debug("USB: Setting up EHCI controller... "); - - // enable controller bus mastering - cmd = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, - cmd | PCI_COMMAND_IO | PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER | PCI_COMMAND_INVALIDATE); - - printk_debug("done.\n"); -} - -static struct device_operations ohci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ohci_init, - .scan_bus = 0, - .enable = southbridge_enable, -}; - -static struct device_operations ehci_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = ehci_init, - .scan_bus = 0, - .enable = southbridge_enable, -}; - -static struct pci_driver cs5536_usb1_driver __pci_driver = { - .ops = &ohci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_OHCI -}; - -static struct pci_driver cs5536_usb2_driver __pci_driver = { - .ops = &ehci_ops, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_CS5536_EHCI -}; -- cgit v1.2.3