From 4086d16ba216955d6124d99c9aae7ceeb2457a71 Mon Sep 17 00:00:00 2001 From: Eric Biederman Date: Thu, 17 Jul 2003 03:26:03 +0000 Subject: - Implement an enable method for pci devices. - Add initial support for the amd8131 - Update the mptable to something possible - hdama/Config add the amd8131 southbridge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@968 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/arima/hdama/mptable.c | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) (limited to 'src/mainboard/arima') diff --git a/src/mainboard/arima/hdama/mptable.c b/src/mainboard/arima/hdama/mptable.c index faf0711b17..ef1037993f 100644 --- a/src/mainboard/arima/hdama/mptable.c +++ b/src/mainboard/arima/hdama/mptable.c @@ -150,43 +150,43 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) /* PCI Slot 1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|0, 0x04, 0x11); + bus_8131_2, (1<<2)|0, 0x04, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|1, 0x04, 0x12); + bus_8131_2, (1<<2)|1, 0x04, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|2, 0x04, 0x13); + bus_8131_2, (1<<2)|2, 0x04, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (1<<2)|3, 0x04, 0x10); + bus_8131_2, (1<<2)|3, 0x04, 0x0); /* PCI Slot 2 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|0, 0x04, 0x12); + bus_8131_2, (2<<2)|0, 0x04, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|1, 0x04, 0x13); + bus_8131_2, (2<<2)|1, 0x04, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|2, 0x04, 0x10); + bus_8131_2, (2<<2)|2, 0x04, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_2, (2<<2)|3, 0x04, 0x11); + bus_8131_2, (2<<2)|3, 0x04, 0x1); /* PCI Slot 3 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|0, 0x03, 0x11); + bus_8131_1, (1<<2)|0, 0x03, 0x1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|1, 0x03, 0x12); + bus_8131_1, (1<<2)|1, 0x03, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|2, 0x03, 0x13); + bus_8131_1, (1<<2)|2, 0x03, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (1<<2)|3, 0x03, 0x10); + bus_8131_1, (1<<2)|3, 0x03, 0x0); /* PCI Slot 4 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|0, 0x03, 0x12); + bus_8131_1, (2<<2)|0, 0x03, 0x2); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|1, 0x03, 0x13); + bus_8131_1, (2<<2)|1, 0x03, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|2, 0x03, 0x10); + bus_8131_1, (2<<2)|2, 0x03, 0x0); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (2<<2)|3, 0x03, 0x11); + bus_8131_1, (2<<2)|3, 0x03, 0x1); /* PCI Slot 5 */ #warning "FIXME get the irqs right, it's just hacked to work for now" @@ -212,9 +212,9 @@ void *smp_write_config_table(void *v, unsigned long * processor_map) /* On board nics */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (3<<2)|0, 0x03, 0x13); + bus_8131_1, (3<<2)|0, 0x03, 0x3); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_8131_1, (4<<2)|0, 0x03, 0x10); + bus_8131_1, (4<<2)|0, 0x03, 0x0); /* There is no extension information... */ -- cgit v1.2.3