From fa5d0f835b1f3bb8907e616913cbf7b91d09ef26 Mon Sep 17 00:00:00 2001
From: Arthur Heymans <arthur@aheymans.xyz>
Date: Tue, 12 Nov 2019 19:11:50 +0100
Subject: nb/intel/sandybridge: Set up console in bootblock

Change-Id: Ia041b63201b2a4a2fe6ab11e3497c460f88061d1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
---
 src/mainboard/apple/macbookair4_2/romstage.c | 67 ----------------------------
 1 file changed, 67 deletions(-)
 delete mode 100644 src/mainboard/apple/macbookair4_2/romstage.c

(limited to 'src/mainboard/apple/macbookair4_2/romstage.c')

diff --git a/src/mainboard/apple/macbookair4_2/romstage.c b/src/mainboard/apple/macbookair4_2/romstage.c
deleted file mode 100644
index f445eea28e..0000000000
--- a/src/mainboard/apple/macbookair4_2/romstage.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdint.h>
-#include <string.h>
-#include <device/pci_ops.h>
-#include <device/pci_def.h>
-#include <northbridge/intel/sandybridge/sandybridge.h>
-#include <northbridge/intel/sandybridge/raminit_native.h>
-#include <southbridge/intel/bd82x6x/pch.h>
-#include <cbfs.h>
-
-void mainboard_pch_lpc_setup(void)
-{
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3f0f);
-	pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0070);
-	pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000);
-}
-
-void mainboard_late_rcba_config(void)
-{
-	/* Disable devices.  */
-	RCBA32(0x3414) = 0x00000020;
-}
-const struct southbridge_usb_port mainboard_usb_ports[] = {
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-	{ 1, 0, -1 },
-};
-
-void mainboard_config_superio(void)
-{
-}
-
-void mainboard_get_spd(spd_raw_data *spd, bool id_only)
-{
-	void *spd_file;
-	size_t spd_file_len = 0;
-	spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,
-						&spd_file_len);
-	if (spd_file && spd_file_len >= 1024) {
-		int i;
-		for (i = 0; i < 4; i++)
-			memcpy(&spd[i], spd_file + 256 * i, 128);
-	}
-}
-- 
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