From 4d991550b3a38346071da9dbdc0e7e96a6076082 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 19 Jun 2018 17:09:01 +0300 Subject: aopen/dxplplusu: Add romstage timestamps MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Ic6e2a350a976a3fcb421d47a0bf5600df994edc2 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/27163 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/aopen/dxplplusu/romstage.c | 8 ++++++++ 1 file changed, 8 insertions(+) (limited to 'src/mainboard/aopen') diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 6ea1261231..f203dd1f72 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -47,6 +48,9 @@ void mainboard_romstage_entry(unsigned long bist) }, }; + timestamp_init(timestamp_get()); + timestamp_add_now(TS_START_ROMSTAGE); + /* Get the serial port running and print a welcome banner */ lpc47m10x_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); @@ -58,6 +62,8 @@ void mainboard_romstage_entry(unsigned long bist) if (!e7505_mch_is_ready()) { enable_smbus(); + timestamp_add_now(TS_BEFORE_INITRAM); + /* The real MCH initialisation. */ e7505_mch_init(memctrl); @@ -75,6 +81,8 @@ void mainboard_romstage_entry(unsigned long bist) /* Hook for post ECC scrub settings and debug. */ e7505_mch_done(memctrl); + + timestamp_add_now(TS_AFTER_INITRAM); } printk(BIOS_DEBUG, "SDRAM is up.\n"); -- cgit v1.2.3