From 408d3928236f275633f8656cc12e32949d304d9f Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Fri, 17 Jun 2016 10:43:48 +0300 Subject: intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOP MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/15228 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/aopen/dxplplusu/romstage.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/mainboard/aopen/dxplplusu/romstage.c') diff --git a/src/mainboard/aopen/dxplplusu/romstage.c b/src/mainboard/aopen/dxplplusu/romstage.c index 1e78a979a3..5e7a15958a 100644 --- a/src/mainboard/aopen/dxplplusu/romstage.c +++ b/src/mainboard/aopen/dxplplusu/romstage.c @@ -20,6 +20,7 @@ #include #include #include +#include #include #include @@ -34,8 +35,7 @@ int spd_read_byte(unsigned device, unsigned address) return smbus_read_byte(device, address); } -#include -void main(unsigned long bist) +void mainboard_romstage_entry(unsigned long bist) { static const struct mem_controller memctrl[] = { { -- cgit v1.2.3