From 3aff1a32087137169fb4165eb2dd11655de27f45 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Wed, 11 Apr 2012 12:19:03 +0300
Subject: Convert AOpen DXPL Plus mainboard to CAR
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Tested on real hardware, mainboard with dual Xeon P4 HT CPUs
requires cache-as-ram init code with AP SIPI protocol.

Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI.

Change-Id: I415482f3af22df79d82492c49aed83549f29aa56
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/886
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
---
 src/mainboard/aopen/dxplplusu/dsdt.asl | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/aopen/dxplplusu/dsdt.asl')

diff --git a/src/mainboard/aopen/dxplplusu/dsdt.asl b/src/mainboard/aopen/dxplplusu/dsdt.asl
index 31cfa88ff3..095df060ff 100644
--- a/src/mainboard/aopen/dxplplusu/dsdt.asl
+++ b/src/mainboard/aopen/dxplplusu/dsdt.asl
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <arch/ioapic.h>
+
 DefinitionBlock(
 	"dsdt.aml",
 	"DSDT",
-- 
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