From 3aff1a32087137169fb4165eb2dd11655de27f45 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 11 Apr 2012 12:19:03 +0300 Subject: Convert AOpen DXPL Plus mainboard to CAR MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Tested on real hardware, mainboard with dual Xeon P4 HT CPUs requires cache-as-ram init code with AP SIPI protocol. Also enable 2nd CPU and PATA and clean-up Kconfig and ACPI. Change-Id: I415482f3af22df79d82492c49aed83549f29aa56 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/886 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- src/mainboard/aopen/dxplplusu/Kconfig | 18 ------------------ 1 file changed, 18 deletions(-) (limited to 'src/mainboard/aopen/dxplplusu/Kconfig') diff --git a/src/mainboard/aopen/dxplplusu/Kconfig b/src/mainboard/aopen/dxplplusu/Kconfig index c3025d157a..da03491d87 100644 --- a/src/mainboard/aopen/dxplplusu/Kconfig +++ b/src/mainboard/aopen/dxplplusu/Kconfig @@ -8,8 +8,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select SOUTHBRIDGE_INTEL_I82870 select SOUTHBRIDGE_INTEL_I82801DX select SUPERIO_SMSC_LPC47M10X - select ROMCC - select HAVE_HARD_RESET # select HAVE_PIRQ_TABLE # select PIRQ_ROUTE select UDELAY_TSC @@ -24,14 +22,6 @@ config MAINBOARD_PART_NUMBER string default "DXPL Plus-U" -config DCACHE_RAM_BASE - hex - default 0xcf000 - -config DCACHE_RAM_SIZE - hex - default 0x1000 - config IRQ_SLOT_COUNT int default 12 @@ -40,18 +30,10 @@ config BOARD_HAS_FADT bool default y -config LOGICAL_CPUS - bool - default n - config MAX_CPUS int default 4 -config MAX_PHYSICAL_CPUS - int - default 2 - config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID hex default 0x0 -- cgit v1.2.3