From f95911ad3765c0f94db241b0c95a6c0a8c608077 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 24 Jun 2017 21:45:13 -0600 Subject: mainboard/[a-e]: add IS_ENABLED() around Kconfig symbol references Change-Id: Icca8bac5e67f83dfc5a8f5ef1cb87c6432e0a236 Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/20342 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/amd/bettong/BiosCallOuts.c | 2 +- src/mainboard/amd/bimini_fam10/romstage.c | 4 ++-- src/mainboard/amd/dbm690t/romstage.c | 2 +- src/mainboard/amd/dinar/rd890_cfg.h | 4 ++-- src/mainboard/amd/dinar/sb700_cfg.h | 8 ++++---- src/mainboard/amd/gardenia/BiosCallOuts.c | 2 +- src/mainboard/amd/inagua/broadcom.c | 20 ++++++++++---------- src/mainboard/amd/mahogany/romstage.c | 2 +- src/mainboard/amd/mahogany_fam10/romstage.c | 4 ++-- src/mainboard/amd/parmer/buildOpts.c | 2 +- src/mainboard/amd/pistachio/romstage.c | 2 +- src/mainboard/amd/serengeti_cheetah/mptable.c | 2 +- src/mainboard/amd/serengeti_cheetah/romstage.c | 6 +++--- src/mainboard/amd/serengeti_cheetah_fam10/mptable.c | 2 +- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 4 ++-- src/mainboard/amd/thatcher/buildOpts.c | 2 +- src/mainboard/amd/tilapia_fam10/romstage.c | 4 ++-- src/mainboard/amd/torpedo/Oem.h | 2 +- src/mainboard/amd/torpedo/platform_cfg.h | 4 ++-- 19 files changed, 39 insertions(+), 39 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/bettong/BiosCallOuts.c b/src/mainboard/amd/bettong/BiosCallOuts.c index 15c4b9f792..0df8dc58f3 100644 --- a/src/mainboard/amd/bettong/BiosCallOuts.c +++ b/src/mainboard/amd/bettong/BiosCallOuts.c @@ -83,7 +83,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) #endif /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE +#if IS_ENABLED(CONFIG_HUDSON_XHCI_ENABLE) FchParams_env->Usb.Xhci0Enable = TRUE; #else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index cdb12e3244..53cc64855d 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -136,7 +136,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -150,7 +150,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb800_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index b4a3d1266f..5c841cb3a9 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -88,7 +88,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/dinar/rd890_cfg.h b/src/mainboard/amd/dinar/rd890_cfg.h index 86455539a4..ac3c8182a3 100644 --- a/src/mainboard/amd/dinar/rd890_cfg.h +++ b/src/mainboard/amd/dinar/rd890_cfg.h @@ -28,10 +28,10 @@ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0. */ #ifndef DEFAULT_HT_PATH -#if CONFIG_CPU_AMD_AGESA_FAMILY10 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY10) #define DEFAULT_HT_PATH {0x0, 0x3} #endif -#if CONFIG_CPU_AMD_AGESA_FAMILY15 +#if IS_ENABLED(CONFIG_CPU_AMD_AGESA_FAMILY15) #define DEFAULT_HT_PATH {0x0, 0x1} #endif #endif diff --git a/src/mainboard/amd/dinar/sb700_cfg.h b/src/mainboard/amd/dinar/sb700_cfg.h index 02c3934bfe..1896d11764 100644 --- a/src/mainboard/amd/dinar/sb700_cfg.h +++ b/src/mainboard/amd/dinar/sb700_cfg.h @@ -36,13 +36,13 @@ * before AGESA module get call. */ #ifndef BIOS_SIZE -#if CONFIG_COREBOOT_ROMSIZE_KB_1024 +#if IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_1024) #define BIOS_SIZE BIOS_SIZE_1M -#elif CONFIG_COREBOOT_ROMSIZE_KB_2048 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_2048) #define BIOS_SIZE BIOS_SIZE_2M -#elif CONFIG_COREBOOT_ROMSIZE_KB_4096 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_4096) #define BIOS_SIZE BIOS_SIZE_4M -#elif CONFIG_COREBOOT_ROMSIZE_KB_8192 == 1 +#elif IS_ENABLED(CONFIG_COREBOOT_ROMSIZE_KB_8192) #define BIOS_SIZE BIOS_SIZE_8M #endif #endif diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index a90ad69833..2c87ccec19 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -97,7 +97,7 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr) #endif /* XHCI configuration */ -#if CONFIG_STONEYRIDGE_XHCI_ENABLE +#if IS_ENABLED(CONFIG_STONEYRIDGE_XHCI_ENABLE) FchParams_env->Usb.Xhci0Enable = TRUE; #else FchParams_env->Usb.Xhci0Enable = FALSE; diff --git a/src/mainboard/amd/inagua/broadcom.c b/src/mainboard/amd/inagua/broadcom.c index 9f140a2ce1..f1c49d204f 100644 --- a/src/mainboard/amd/inagua/broadcom.c +++ b/src/mainboard/amd/inagua/broadcom.c @@ -37,7 +37,7 @@ void broadcom_init(void); #define be(x) cpu_to_be32(x) //this is used a lot! /* C forces us to specify these before defining struct selfboot_patch :-( */ -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) #define INIT1_LENGTH 9 #define INIT2_LENGTH 10 #define INIT3_LENGTH 3 @@ -179,7 +179,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .powerdown.padding = be16(0x0000), /* Only the lines below may be adapted to your needs ... */ -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .header.mac_addr = { 0x00, 0x10, 0x18, 0x00, 0x00, 0x00 }, //Broadcom .header.subsys_device = be16(0x1699), //same as pci_device .header.subsys_vendor = be16(0x14E4), //Broadcom @@ -189,7 +189,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .header.subsys_vendor = be16(0x121D), //LiPPERT #endif .header.pci_device = be16(0x1699), //Broadcom 5785 with GbE PHY -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .header.patch_version = be16(0x010B), //1.11 (Broadcom's sb5785m1.11) #else .header.patch_version = be16(0x110B), //1.11b, i.e. hacked :-) @@ -208,7 +208,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * 1 X 0 | 0x330C5180 - - - * 1 X 1 | 0x391C6140 - - - */ -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .header.basic_config = be16(0x0404), //original for B50610 #else .header.basic_config = be16(0x0604), //bit 9 set so not to mess up PHY regs, kept other bits unchanged @@ -244,7 +244,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! * was added, for reference see Broadcom's changelog. */ .init.hunk1_code = { -#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x082B8104), //CFR-AF: PHY0B: KSZ9021 select PHY104 be(0x082CF0F0), //CFR-AF: PHY0C: KSZ9021 clk/ctl skew (advised by Micrel) be(0x082B8105), //CFR-AF: PHY0B: KSZ9021 select PHY105 @@ -258,7 +258,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .init.hunk2_when = 0x30, //after global reset, PHY reset .init.hunk2_code = { -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x08370F08), //v1.06 : PHY17: B50610 select reg. 08 be(0x08350001), //v1.06 : PHY15: B50610 slow link fix be(0x08370F00), //v1.06 : PHY17: B50610 disable reg. 08 @@ -275,20 +275,20 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! be(0xC1F03604), be(0xFFE0FFFF), be(0x00110000), //v1.08 : 3604.20-16: 10Mb clock = 12.5MHz }, //-->INIT3_LENGTH! -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) .init.hunk4_when = 0xD8, //original for B50610 #else .init.hunk4_when = 0x80, //run last, after Linux' "ifconfig up" #endif .init.hunk4_code = { -#if CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x083F4300), //CFR-AF: PHY1F: IRQ active high be(0x083C0000), //CFR-AF: PHY1C: revert driver writes be(0x08380000), //CFR-AF: PHY18| be(0x083C0000), //CFR-AF: PHY1C| #endif be(0xCB0005A4), be(0xF7F0000C), //v1.01 : if 5A4.0 == 1 -->skip next 12 bytes -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0xC61005A4), be(0x3210C500), //v1.01 : 5A4: PHY LED mode #else be(0xC61005A4), be(0x331C71CE), //CFR-AF: 5A4: fake LED mode @@ -300,7 +300,7 @@ static struct selfboot_patch { //Watch out: all values are *BIG-ENDIAN*! .powerdown.hunk1_when = 0x50, //prior to IDDQ MAC .powerdown.hunk1_code = { -#if !CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF +#if !IS_ENABLED(CONFIG_BOARD_LIPPERT_FRONTRUNNER_AF) be(0x083CB001), //v1.10 : PHY1C: IDDQ B50610 PHY #endif be(0xF7F30116), // IDDQ PHY diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index a8e54d5db7..86cb9ab706 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -91,7 +91,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index efb2885963..03938225aa 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -141,7 +141,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -155,7 +155,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 8ba3c539ba..49a9feb7a9 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -154,7 +154,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 20086193ca..7f04e7f5b9 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -87,7 +87,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ wait_all_core0_started(); start_other_cores(); diff --git a/src/mainboard/amd/serengeti_cheetah/mptable.c b/src/mainboard/amd/serengeti_cheetah/mptable.c index fc421a9eae..0210368a3e 100644 --- a/src/mainboard/amd/serengeti_cheetah/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah/mptable.c @@ -17,7 +17,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include #endif #include diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 73a1e9f133..17ac940957 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -104,7 +104,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) struct cpuid_result cpuid1; #endif @@ -127,7 +127,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) setup_coherent_ht_domain(); /* routing table and start other core0 */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* It is said that we should start core1 after all core0 launched */ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, @@ -140,7 +140,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); /* it will init sblnk and sbbusn, nodes, sbdn */ -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c index d800051216..048e800603 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/mptable.c @@ -19,7 +19,7 @@ #include #include #include -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) #include #endif #include diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 831e050648..e130ebd78a 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -242,7 +242,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); - #if CONFIG_LOGICAL_CPUS + #if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -252,7 +252,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x38); - #if CONFIG_SET_FIDVID + #if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 8ed3bf2fdc..7bc5a7789c 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -154,7 +154,7 @@ #define BLDCFG_LVDS_POWER_ON_SEQ_VARY_BL_TO_BLON 3 #define BLDCFG_LVDS_POWER_ON_SEQ_BLON_TO_VARY_BL 3 -#if CONFIG_GFXUMA +#if IS_ENABLED(CONFIG_GFXUMA) #define BLDCFG_UMA_ALIGNMENT UMA_4MB_ALIGNED #define BLDCFG_UMA_ALLOCATION_MODE UMA_SPECIFIED //#define BLDCFG_UMA_ALLOCATION_SIZE 0x1000//0x1800//0x1000 /* (1000 << 16) = 256M*/ diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index 022e91de19..92fee4562c 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -137,7 +137,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) */ wait_all_core0_started(); -#if CONFIG_LOGICAL_CPUS +#if IS_ENABLED(CONFIG_LOGICAL_CPUS) /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(bsp_apicid); @@ -151,7 +151,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs780_early_setup(); sb7xx_51xx_early_setup(); -#if CONFIG_SET_FIDVID +#if IS_ENABLED(CONFIG_SET_FIDVID) msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); diff --git a/src/mainboard/amd/torpedo/Oem.h b/src/mainboard/amd/torpedo/Oem.h index 0910ddc257..f8f9d80502 100644 --- a/src/mainboard/amd/torpedo/Oem.h +++ b/src/mainboard/amd/torpedo/Oem.h @@ -16,7 +16,7 @@ #define BIOS_SIZE 0x04 //04 - 1MB #endif #define LEGACY_FREE 0x00 -#if !CONFIG_ONBOARD_USB30 +#if !IS_ENABLED(CONFIG_ONBOARD_USB30) #define XHCI_SUPPORT 0x01 #endif diff --git a/src/mainboard/amd/torpedo/platform_cfg.h b/src/mainboard/amd/torpedo/platform_cfg.h index 0713e41e29..72a97d1322 100644 --- a/src/mainboard/amd/torpedo/platform_cfg.h +++ b/src/mainboard/amd/torpedo/platform_cfg.h @@ -294,7 +294,7 @@ #define INCHIP_USB_CINFIG 0x7F #define INCHIP_USB_OHCI1_CINFIG 0x01 #define INCHIP_USB_OHCI2_CINFIG 0x01 -#if CONFIG_ONBOARD_USB30 +#if IS_ENABLED(CONFIG_ONBOARD_USB30) #define INCHIP_USB_OHCI3_CINFIG 0x00 #else #define INCHIP_USB_OHCI3_CINFIG 0x01 @@ -962,7 +962,7 @@ * @li 0 - Disable * @li 1 - Enable */ -#if CONFIG_ONBOARD_USB30 +#if IS_ENABLED(CONFIG_ONBOARD_USB30) #define SB_XHCI_SWITCH 0 #else #define SB_XHCI_SWITCH 1 -- cgit v1.2.3