From e8b4da2f6f8b6fc38db82b1a2e1b9b9340ecfc53 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Tue, 21 Oct 2014 18:22:32 +0300 Subject: AMD: Isolate AGESA and PI build environments for southbridge MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To backport features introduced with recent Chromebooks and/or Intel boards in general, heavy work on the AMD AGESA platform infrastructure is required. With the AGESA PI available in binary form only, community members have little means to verify, debug and develop for the said platforms. Thus it makes sense to fork the existing agesawrapper interfaces, to give AMD PI platforms a clean and independent sandbox. New directory layout reflects the separation already taken place under 3rdparty/ and vendorcode/. Change-Id: Ia730f0e45e7c1bdfc0c91e95eb6729a77773e2b9 Signed-off-by: Kyösti Mälkki Reviewed-on: http://review.coreboot.org/7388 Reviewed-by: Edward O'Callaghan Reviewed-by: Bruce Griffith Tested-by: build bot (Jenkins) --- src/mainboard/amd/olivehillplus/Kconfig | 2 +- src/mainboard/amd/olivehillplus/devicetree.cb | 4 ++-- src/mainboard/amd/olivehillplus/dsdt.asl | 10 +++++----- src/mainboard/amd/olivehillplus/mptable.c | 2 +- src/mainboard/amd/olivehillplus/romstage.c | 2 +- 5 files changed, 10 insertions(+), 10 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/olivehillplus/Kconfig b/src/mainboard/amd/olivehillplus/Kconfig index 6191cb1070..93f0fc68a9 100644 --- a/src/mainboard/amd/olivehillplus/Kconfig +++ b/src/mainboard/amd/olivehillplus/Kconfig @@ -23,7 +23,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_AMD_PI_00730F01 select NORTHBRIDGE_AMD_PI_00730F01 - select SOUTHBRIDGE_AMD_AGESA_AVALON + select SOUTHBRIDGE_AMD_PI_AVALON select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb index aec71f9d72..3c5e38f4cd 100644 --- a/src/mainboard/amd/olivehillplus/devicetree.cb +++ b/src/mainboard/amd/olivehillplus/devicetree.cb @@ -39,7 +39,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 2.5 on end # Edge Connector end #chip northbridge/amd/pi/00730F01 - chip southbridge/amd/agesa/hudson # it is under NB/SB Link, but on the same pci bus + chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus device pci 10.0 on end # XHCI HC0 device pci 11.0 on end # SATA device pci 12.0 on end # USB @@ -57,7 +57,7 @@ chip northbridge/amd/pi/00730F01/root_complex device pci 14.2 on end # HDA 0x4383 device pci 14.3 on end # LPC 0x439d device pci 14.7 on end # SD - end #chip southbridge/amd/hudson + end #chip southbridge/amd/pi/avalon device pci 18.0 on end device pci 18.1 on end diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl index b74dac6218..56381e18f3 100644 --- a/src/mainboard/amd/olivehillplus/dsdt.asl +++ b/src/mainboard/amd/olivehillplus/dsdt.asl @@ -37,13 +37,13 @@ DefinitionBlock ( #include "acpi/usb_oc.asl" /* PCI IRQ mapping for the Southbridge */ - #include + #include /* Describe the processor tree (\_PR) */ #include /* Contains the supported sleep states for this chipset */ - #include + #include /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ #include "acpi/sleep.asl" @@ -68,16 +68,16 @@ DefinitionBlock ( #include /* Describe the AMD Fusion Controller Hub Southbridge */ - #include + #include } /* Describe PCI INT[A-H] for the Southbridge */ - #include + #include } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ - #include + #include /* Define the General Purpose Events for the platform */ #include "acpi/gpe.asl" diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c index 73660e4543..80ba5b5af7 100644 --- a/src/mainboard/amd/olivehillplus/mptable.c +++ b/src/mainboard/amd/olivehillplus/mptable.c @@ -27,7 +27,7 @@ #include #include #include -#include /* pm_ioread() */ +#include /* pm_ioread() */ u8 picr_data[0x54] = { 0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index 5230f7dfa3..a7c825d756 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -34,7 +34,7 @@ #include #include "cpu/x86/bist.h" #include "cpu/x86/lapic.h" -#include "southbridge/amd/agesa/hudson/hudson.h" +#include "southbridge/amd/pi/avalon/hudson.h" #include "cpu/amd/pi/s3_resume.h" void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) -- cgit v1.2.3