From e6315f74d6f402734e476a57a8faf4ac9cb23d38 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 4 Apr 2020 05:27:05 +0200 Subject: mb/amd/mandolin: Add Picasso CRB Mandolin is the CRB for AMD Picasso and Dali. The mainboard code still needs a little cleanup and verification, but I'll do that in a follow-up to have a non Chromebook board using the Picasso SoC code in tree as soon as possible to be able to detect some possible breakage. BUG=b:130660285 Signed-off-by: Marshall Dawson Signed-off-by: Aaron Durbin Signed-off-by: Zheng Bao Signed-off-by: Felix Held Signed-off-by: Furquan Shaikh Change-Id: I2b4a78e1eef9f998e1986da1506201eb505822eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/33772 Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/Kconfig | 94 +++++++ src/mainboard/amd/mandolin/Kconfig.name | 2 + src/mainboard/amd/mandolin/Makefile.inc | 31 +++ src/mainboard/amd/mandolin/acpi/gpe.asl | 65 +++++ src/mainboard/amd/mandolin/acpi/mainboard.asl | 15 ++ src/mainboard/amd/mandolin/acpi/sleep.asl | 73 ++++++ src/mainboard/amd/mandolin/board_info.txt | 1 + src/mainboard/amd/mandolin/bootblock.c | 19 ++ src/mainboard/amd/mandolin/devicetree.cb | 85 +++++++ src/mainboard/amd/mandolin/dsdt.asl | 52 ++++ src/mainboard/amd/mandolin/early_gpio.c | 36 +++ src/mainboard/amd/mandolin/gpio.c | 61 +++++ src/mainboard/amd/mandolin/gpio.h | 9 + src/mainboard/amd/mandolin/hda_verb.c | 97 ++++++++ src/mainboard/amd/mandolin/mainboard.c | 339 ++++++++++++++++++++++++++ src/mainboard/amd/mandolin/mandolin.fmd | 8 + src/mainboard/amd/mandolin/romstage.c | 1 + 17 files changed, 988 insertions(+) create mode 100644 src/mainboard/amd/mandolin/Kconfig create mode 100644 src/mainboard/amd/mandolin/Kconfig.name create mode 100644 src/mainboard/amd/mandolin/Makefile.inc create mode 100644 src/mainboard/amd/mandolin/acpi/gpe.asl create mode 100644 src/mainboard/amd/mandolin/acpi/mainboard.asl create mode 100644 src/mainboard/amd/mandolin/acpi/sleep.asl create mode 100644 src/mainboard/amd/mandolin/board_info.txt create mode 100644 src/mainboard/amd/mandolin/bootblock.c create mode 100644 src/mainboard/amd/mandolin/devicetree.cb create mode 100644 src/mainboard/amd/mandolin/dsdt.asl create mode 100644 src/mainboard/amd/mandolin/early_gpio.c create mode 100644 src/mainboard/amd/mandolin/gpio.c create mode 100644 src/mainboard/amd/mandolin/gpio.h create mode 100644 src/mainboard/amd/mandolin/hda_verb.c create mode 100644 src/mainboard/amd/mandolin/mainboard.c create mode 100644 src/mainboard/amd/mandolin/mandolin.fmd create mode 100644 src/mainboard/amd/mandolin/romstage.c (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig new file mode 100644 index 0000000000..9760e45194 --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig @@ -0,0 +1,94 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if BOARD_AMD_MANDOLIN + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_COMMON_BLOCK_USE_ESPI + select SOC_AMD_PICASSO + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select AZALIA_PLUGIN_SUPPORT + select HAVE_ACPI_RESUME + +config FMDFILE + string + default "src/mainboard/amd/mandolin/mandolin.fmd" + +config AMD_LPC_DEBUG_CARD + bool "Enable LPC-Serial debug card on the debug header" + default n + select PICASSO_LPC_IOMUX + select SUPERIO_SMSC_SIO1036 + help + AMD's debug card contains an SMSC SIO1036 device which provides + an I/O-based UART in the system. This feature is not compatible with + CONFIG_HUDSON_UART enabling the memory-mapped UART in the chipset. + Note that Kconfig does not currently enforce this restriction. + +config CBFS_SIZE + default 0x780000 + help + TODO: Adjust this to maximize CBFS size + +config MAINBOARD_DIR + string + default amd/mandolin + +config MAINBOARD_PART_NUMBER + string + default "MANDOLIN" + +config MAX_CPUS + int + default 8 + +config IRQ_SLOT_COUNT + int + default 11 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config AMD_FWM_POSITION_INDEX + int + default 3 + help + TODO: might need to be adapted for better placement of files in cbfs + +config MANDOLIN_HAVE_MCHP_FW + bool "Have Microchip EC firmware?" + default n + +config MANDOLIN_MCHP_FW_FILE + string + depends on MANDOLIN_HAVE_MCHP_FW + default "3rdparty/blobs/mainboard/amd/mandolin/mchp.bin" + +if !AMD_LPC_DEBUG_CARD +choice MANDOLIN_LPC_IOMUX + prompt "State of IOMux for LPC/eMMC signals" + default MANDOLIN_IOMUX_USE_EMMC + help + Mandolin is designed to use either LPC or eMMC signals. Use this + selection to determine which are configured for this image. + +config MANDOLIN_IOMUX_USE_LPC + bool "LPC signals" + help + +config MANDOLIN_IOMUX_USE_EMMC + bool "eMMC signals" + +endchoice +endif # !AMD_LPC_DEBUG_CARD + +config PICASSO_LPC_IOMUX + bool + default y if MANDOLIN_IOMUX_USE_LPC + help + Picasso's LPC bus signals are MUXed with some of the EMMC signals. + Select this option if LPC signals are required. + +endif # BOARD_AMD_MANDOLIN diff --git a/src/mainboard/amd/mandolin/Kconfig.name b/src/mainboard/amd/mandolin/Kconfig.name new file mode 100644 index 0000000000..7dbfc3fd71 --- /dev/null +++ b/src/mainboard/amd/mandolin/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_MANDOLIN + bool "Mandolin" diff --git a/src/mainboard/amd/mandolin/Makefile.inc b/src/mainboard/amd/mandolin/Makefile.inc new file mode 100644 index 0000000000..52ad9c695b --- /dev/null +++ b/src/mainboard/amd/mandolin/Makefile.inc @@ -0,0 +1,31 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c +bootblock-y += early_gpio.c + +ramstage-y += gpio.c + +# APCB_mandolin.bin +APCB_SOURCES = mandolin + +PHONY+=add_mchp_fw +INTERMEDIATE+=add_mchp_fw + +ifeq ($(CONFIG_MANDOLIN_HAVE_MCHP_FW),y) + +MANDOLIN_MICROCHIP_FW_OFFSET=0 +add_mchp_fw: $(obj)/coreboot.pre + $(CBFSTOOL) $(obj)/coreboot.pre write -r EC -f $(CONFIG_MANDOLIN_MCHP_FW_FILE) --fill-upward + +else +files_added:: warn_no_mchp +endif # CONFIG_MANDOLIN_HAVE_MCHP_FW + +PHONY+=warn_no_mchp +warn_no_mchp: + printf "\n\t** WARNING **\n" + printf "coreboot has been built without an the Microchip EC.\n" + printf "Do not flash this image. Your Mandolin's power button\n" + printf "will not respond when you press it.\n\n" + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/acpi diff --git a/src/mainboard/amd/mandolin/acpi/gpe.asl b/src/mainboard/amd/mandolin/acpi/gpe.asl new file mode 100644 index 0000000000..e28edf84ba --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/gpe.asl @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +// +// +// +// todo: check file for accuracy +// +// +// + +External (\_SB.PCI0.PBR4, DeviceObj) +External (\_SB.PCI0.PBR5, DeviceObj) +External (\_SB.PCI0.PBR6, DeviceObj) +External (\_SB.PCI0.PBR7, DeviceObj) +External (\_SB.PCI0.AZHD, DeviceObj) + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.EHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.XHC0, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.PBR7, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/amd/mandolin/acpi/mainboard.asl b/src/mainboard/amd/mandolin/acpi/mainboard.asl new file mode 100644 index 0000000000..d59240bc16 --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Memory related values */ +Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ +Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ +Name(PBLN, 0x0) /* Length of BIOS area */ + +Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ +Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ +Name(HPBA, 0xFED00000) /* Base address of HPET table */ + +/* Some global data */ +Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ +Name(OSV, Ones) /* Assume nothing */ +Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/amd/mandolin/acpi/sleep.asl b/src/mainboard/amd/mandolin/acpi/sleep.asl new file mode 100644 index 0000000000..0b65ab19ef --- /dev/null +++ b/src/mainboard/amd/mandolin/acpi/sleep.asl @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear wake status structure. */ + Store(0, PEWD) + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + Store(7, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/amd/mandolin/board_info.txt b/src/mainboard/amd/mandolin/board_info.txt new file mode 100644 index 0000000000..b351b8e696 --- /dev/null +++ b/src/mainboard/amd/mandolin/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/mandolin/bootblock.c b/src/mainboard/amd/mandolin/bootblock.c new file mode 100644 index 0000000000..06da379d93 --- /dev/null +++ b/src/mainboard/amd/mandolin/bootblock.c @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include "gpio.h" + +#define SERIAL_DEV PNP_DEV(0x4e, SIO1036_SP1) + +void bootblock_mainboard_early_init(void) +{ + mainboard_program_early_gpios(); + + if (CONFIG(SUPERIO_SMSC_SIO1036)) { + lpc_enable_sio_decode(LPC_SELECT_SIO_4E4F); + lpc_enable_decode(DECODE_ENABLE_SERIAL_PORT0 << CONFIG_UART_FOR_CONSOLE); + sio1036_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + } +} diff --git a/src/mainboard/amd/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/devicetree.cb new file mode 100644 index 0000000000..179582b673 --- /dev/null +++ b/src/mainboard/amd/mandolin/devicetree.cb @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/amd/picasso + register "acp_pin_cfg" = "I2S_PINS_MAX_HDA" + + # Set FADT Configuration + register "fadt_pm_profile" = "PM_UNSPECIFIED" + register "fadt_boot_arch" = "ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042" + register "fadt_flags" = "ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON" + + register "sd_emmc_config" = "SD_EMMC_DISABLE" + + # eSPI Configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0X60_0X64_EN, + .generic_io_range[0] = { + .base = 0x662, + .size = 8, + }, + + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .dedicated_alert_pin = 1, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + + device cpu_cluster 0 on + device lapic 0 on end + end + device domain 0 on + subsystemid 0x1022 0x1510 inherit + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Dummy Host Bridge + device pci 1.3 on end # Bridge + device pci 8.0 on end # Dummy Host Bridge + device pci 8.1 on # Bridge to Bus A + device pci 0.0 on end # Internal GPU + device pci 0.1 on end # Display HDA + device pci 0.2 on end # Crypto Coprocesor + device pci 0.3 on end # USB 3.1 + device pci 0.4 on end # USB 3.1 + device pci 0.5 on end # Audio + device pci 0.6 on end # HDA + device pci 0.7 on end # non-Sensor Fusion Hub device + end + device pci 8.2 on # Bridge to Bus B + device pci 0.0 on end # AHCI + device pci 0.1 on end # Ethernet + device pci 0.2 on end # Ethernet + end + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 50 on end + device i2c 51 on end + end + end # SM + device pci 14.3 on # - D14F3 bridge + chip superio/smsc/sio1036 # optional debug card + end + end + device pci 14.6 off end # SDHCI + device pci 18.0 on end # Data fabric [0-7] + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + device pci 18.6 on end + device pci 18.7 on end + end # domain +end # chip soc/amd/picasso diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl new file mode 100644 index 0000000000..02a661918f --- /dev/null +++ b/src/mainboard/amd/mandolin/dsdt.asl @@ -0,0 +1,52 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define MAINBOARD_HAS_SPEAKER 1 + +/* DefinitionBlock Statement */ +#include +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include */ /* as needed */ + + /* global NVS and variables */ + #include + + /* Globals for the platform */ + #include "acpi/mainboard.asl" + + /* PCI IRQ mapping for the Southbridge */ + #include + + /* Describe the processor tree (\_PR) */ + #include + + /* Contains the supported sleep states for this chipset */ + #include + + /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ + #include "acpi/sleep.asl" + + /* Contains _SWS methods */ + #include + + /* System Bus */ + Scope(\_SB) { /* Start \_SB scope */ + /* global utility methods expected within the \_SB scope */ + #include + + /* Describe the SOC */ + #include + + } /* End \_SB scope */ + + /* Define the General Purpose Events for the platform */ + #include "acpi/gpe.asl" +} +/* End of ASL file */ diff --git a/src/mainboard/amd/mandolin/early_gpio.c b/src/mainboard/amd/mandolin/early_gpio.c new file mode 100644 index 0000000000..b6dd0d6990 --- /dev/null +++ b/src/mainboard/amd/mandolin/early_gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "gpio.h" + +/* GPIO pins used by coreboot should be initialized in bootblock */ + +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* not LLB */ + PAD_GPI(GPIO_12, PULL_UP), + /* not USB_OC5_L */ + PAD_GPI(GPIO_13, PULL_UP), + /* not USB_OC4_L */ + PAD_GPI(GPIO_14, PULL_UP), + /* not USB_OC1_L */ + PAD_GPI(GPIO_17, PULL_UP), + /* not USB_OC2_L */ + PAD_GPI(GPIO_18, PULL_UP), + /* SDIO eMMC power control */ + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_NONE), + /* PCIe SSD power enable */ + PAD_GPO(GPIO_23, HIGH), + /* PCIe Reset to DP0, DP1, J2105, TP, FP */ + PAD_NF(GPIO_27, PCIE_RST1_L, PULL_NONE), + /* eSPI CS# */ + PAD_NF(GPIO_30, ESPI_CS_L, PULL_NONE), + /* FANOUT0 */ + PAD_NF(GPIO_85, FANOUT0, PULL_NONE), + /* PC beep to codec */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +void mainboard_program_early_gpios(void) +{ + program_gpios(gpio_set_stage_reset, ARRAY_SIZE(gpio_set_stage_reset)); +} diff --git a/src/mainboard/amd/mandolin/gpio.c b/src/mainboard/amd/mandolin/gpio.c new file mode 100644 index 0000000000..a60f00e03a --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.c @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_ram[] = { + /* SSD DEVSLP */ + PAD_NF(GPIO_5, DEVSLP0, PULL_NONE), + /* Defeature SATA Express DEVSLP, as some boards are reworked + * to tie this to GPIO23 to control power */ + PAD_GPI(GPIO_6, PULL_UP), + /* I2S SDIN */ + PAD_NF(GPIO_7, ACP_I2S_SDIN, PULL_NONE), + /* I2S LRCLK */ + PAD_NF(GPIO_8, ACP_I2S_LRCLK, PULL_NONE), + /* Blink */ + PAD_NF(GPIO_11, BLINK, PULL_NONE), + /* APU_ALS_INT# */ + PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), + /* Finger print CS# */ + PAD_GPO(GPIO_31, HIGH), + /* NFC IRQ */ + PAD_INT(GPIO_69, PULL_UP, EDGE_LOW, STATUS), + /* Rear camera power enable */ + PAD_GPO(GPIO_89, HIGH), +}; + +/* eMMC controller driving either an SD card or eMMC device. */ +static const struct soc_amd_gpio emmc_gpios[] = { + PAD_NF(GPIO_21, EMMC_CMD, PULL_UP), + PAD_NF(GPIO_22, EMMC_PRW_CTRL, PULL_UP), + PAD_NF(GPIO_68, EMMC_CD, PULL_UP), + PAD_NF(GPIO_70, EMMC_CLK, PULL_NONE), + PAD_NF(GPIO_104, EMMC_DATA0, PULL_UP), + PAD_NF(GPIO_105, EMMC_DATA1, PULL_UP), + PAD_NF(GPIO_106, EMMC_DATA2, PULL_UP), + PAD_NF(GPIO_107, EMMC_DATA3, PULL_NONE), + PAD_NF(GPIO_74, EMMC_DATA4, PULL_UP), + PAD_NF(GPIO_75, EMMC_DATA6, PULL_UP), + PAD_NF(GPIO_87, EMMC_DATA7, PULL_UP), + PAD_NF(GPIO_88, EMMC_DATA5, PULL_UP), + PAD_NF(GPIO_109, EMMC_DS, PULL_UP), +}; + +void mainboard_program_gpios(void) +{ + program_gpios(gpio_set_stage_ram, ARRAY_SIZE(gpio_set_stage_ram)); + + /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */ + if (CONFIG(AMD_LPC_DEBUG_CARD)) + printk(BIOS_INFO, "eMMC not available due to LPC requirement\n"); + else + program_gpios(emmc_gpios, ARRAY_SIZE(emmc_gpios)); +} diff --git a/src/mainboard/amd/mandolin/gpio.h b/src/mainboard/amd/mandolin/gpio.h new file mode 100644 index 0000000000..04c98c50df --- /dev/null +++ b/src/mainboard/amd/mandolin/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_program_early_gpios(void); /* bootblock GPIO configuration */ +void mainboard_program_gpios(void); /* ramstage GPIO configuration */ + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/amd/mandolin/hda_verb.c b/src/mainboard/amd/mandolin/hda_verb.c new file mode 100644 index 0000000000..61ae400540 --- /dev/null +++ b/src/mainboard/amd/mandolin/hda_verb.c @@ -0,0 +1,97 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek ALC701 */ + 0x10ec0701, + 0x00000000, + 0x00000016, + + AZALIA_SUBVENDOR(0, 0x1022D001), // HDA Codec Subsystem ID: 0x1022D001 + + 0x0017ff00, 0x0017ff00, 0x0017ff00, 0x0017ff00, // Widget node 0x01 : + 0x01271c40, 0x01271d01, 0x01271ea6, 0x01271fb7, // Pin widget 0x12 - DMIC + 0x01371c00, 0x01371d00, 0x01371e00, 0x01371f40, // Pin widget 0x13 - DMIC + 0x01471c10, 0x01471d01, 0x01471e17, 0x01471f90, // Pin widget 0x14 - FRONT (Port-D) + 0x01571cf0, 0x01571d11, 0x01571e11, 0x01571f41, // Pin widget 0x15 - I2S-OUT + 0x01671cf0, 0x01671d11, 0x01671e11, 0x01671f41, // Pin widget 0x16 - LINE3 (Port-B) + 0x01771cf0, 0x01771d11, 0x01771e11, 0x01771f41, // Pin widget 0x17 - I2S-OUT + 0x01871cf0, 0x01871d11, 0x01871e11, 0x01871f41, // Pin widget 0x18 - I2S-IN + 0x01971cf0, 0x01971d11, 0x01971e11, 0x01971f41, // Pin widget 0x19 - MIC2 (Port-F) + 0x01a71cf0, 0x01a71d11, 0x01a71e11, 0x01a71f41, // Pin widget 0x1A - LINE1 (Port-C) + 0x01b71c50, 0x01b71d10, 0x01b71ea1, 0x01b71f04, // Pin widget 0x1B - LINE2 (Port-E) + 0x01d71c01, 0x01d71d00, 0x01d71e60, 0x01d71f40, // Pin widget 0x1D - PC-BEEP + 0x01e71c30, 0x01e71d11, 0x01e71e45, 0x01e71f04, // Pin widget 0x1E - S/PDIF-OUT + 0x01f71cf0, 0x01f71d11, 0x01f71e11, 0x01f71f41, // Pin widget 0x1F - S/PDIF-IN + 0x02171c20, 0x02171d10, 0x02171e21, 0x02171f04, // Pin widget 0x21 - HP-OUT (Port-I) + 0x02971cf0, 0x02971d11, 0x02971e11, 0x02971f41, // Pin widget 0x29 - I2S-IN + 0x02050038, 0x02047901, 0x0205006b, 0x02040260, // NID 0x20 -0 Set Class-D output + // power as 2.2W@4 Ohm, and + // MIC2-VREFO-R is controlled by + // Line2 port. + 0x0205001a, 0x02048c03, 0x02050045, 0x0204b289, // NID 0x20 - 1 + 0x0205004a, 0x0204201b, 0x0205004a, 0x0204201b, // NID 0x20 - 2 + 0x02050010, 0x02040420, 0x01470c00, 0x02050036, // Dos beep path - 1 + 0x02047151, 0x01470740, 0x0143b000, 0x01470c02, // Dos beep path - 2 + + /* Realtek ALC285 */ + 0x10ec0285, + 0x00000000, + 0x00000028, + + AZALIA_SUBVENDOR(0, 0x1022D002), + + 0x0017ff00, 0x0017ff00, 0x0017ff00, 0x0017ff00, // Widget node 0x01 : + 0x01271c40, 0x01271d01, 0x01271ea6, 0x01271fb7, // Pin widget 0x12 - DMIC + 0x01371c00, 0x01371d00, 0x01371e00, 0x01371f40, // Pin widget 0x13 - DMIC + 0x01471c10, 0x01471d01, 0x01471e17, 0x01471f90, // Pin widget 0x14 - Front (Port-D) + 0x01671cf0, 0x01671d11, 0x01671e11, 0x01671f41, // Pin widget 0x16 - NPC + 0x01771cf0, 0x01771d11, 0x01771e11, 0x01771f41, // Pin widget 0x17 - I2S OUT + 0x01871cf0, 0x01871d11, 0x01871e11, 0x01871f41, // Pin widget 0x18 - I2S IN + 0x01971cf0, 0x01971d11, 0x01971e11, 0x01971f41, // Pin widget 0x19 - MIC2 (Port-F) + 0x01a71cf0, 0x01a71d11, 0x01a71e11, 0x01a71f41, // Pin widget 0x1A - NPC + 0x01b71c30, 0x01b71d90, 0x01b71ea1, 0x01b71f04, // Pin widget 0x1B - LINE2 (Port-E) + 0x01d71c2d, 0x01d71d19, 0x01d71e66, 0x01d71f40, // Pin widget 0x1D - BEEP-IN + 0x01e71cf0, 0x01e71d11, 0x01e71e11, 0x01e71f41, // Pin widget 0x1E - S/PDIF-OUT + 0x02171c20, 0x02171d10, 0x02171e21, 0x02171f04, // Pin widget 0x21 - HP1-OUT (Port-I) + 0x05c50011, 0x05c40003, 0x05c50011, 0x05c40003, // dis. Silence detect delay turn off + 0x0205003c, 0x0204f254, 0x0205003c, 0x0204f214, // Class-D power on reset + 0x02050045, 0x0204b009, 0x02050063, 0x02040020, // Set TRS + turn off MIC2 VREFO + // gating with HP-JD. + 0x0205004a, 0x020420b0, 0x02050009, 0x02043803, // Enable HP JD + Set JD2 to 1 port + // JD for WoV + 0x0205000b, 0x0204777a, 0x0205000b, 0x0204777a, // Set TRS + Set JD2 pull up. + 0x02050038, 0x02043909, 0x05c50000, 0x05c43482, // NID 0x20 set class-D to 2W@4ohm + // (+12dB gain) + Set sine + // tone gain(0x34) + 0x05350000, 0x0534002a, 0x05350000, 0x0534002a, // Disable EQ + set 100Hz 2nd High + // Pass filter + 0x0535001d, 0x05340800, 0x0535001e, 0x05340800, // Left Channel-1 + 0x05350005, 0x053403f6, 0x05350006, 0x0534854c, // Left Channel-2 + 0x05350007, 0x05341e09, 0x05350008, 0x05346472, // Left Channel-3 + 0x05350009, 0x053401fb, 0x0535000a, 0x05344836, // Left Channel-4 + 0x0535000b, 0x05341c00, 0x0535000c, 0x05340000, // Left Channel-5 + 0x0535000d, 0x05340200, 0x0535000e, 0x05340000, // Left Channel-6 + 0x05450000, 0x05440000, 0x0545001d, 0x05440800, // Right Channel-1 + 0x0545001e, 0x05440800, 0x05450005, 0x054403f6, // Right Channel-2 + 0x05450006, 0x0544854c, 0x05450007, 0x05441e09, // Right Channel-3 + 0x05450008, 0x05446472, 0x05450009, 0x054401fb, // Right Channel-4 + 0x0545000a, 0x05444836, 0x0545000b, 0x05441c00, // Right Channel-5 + 0x0545000c, 0x05440000, 0x0545000d, 0x05440200, // Right Channel-6 + 0x0545000e, 0x05440000, 0x05350000, 0x0534c02a, // Right Channel-7+ EQ Update & Enable + 0x05d50006, 0x05d44c50, 0x05d50002, 0x05d46004, // AGC-1 Disable + (Front Gain=0dB ) + 0x05d50003, 0x05d45e5e, 0x05d50001, 0x05d4d783, // AGC-2 (Back Boost Gain = -0.375dB, + // Limiter = -1.125dB) + 0x05d50009, 0x05d451ff, 0x05d50006, 0x05d44e50, // AGC-3 + AGC Enable + 0x02050010, 0x02040020, 0x02050040, 0x02048800, // EAPD set to verb-control. + 0x02050030, 0x02049000, 0x02050037, 0x0204fe15, // Class D silent detection Enable + // -84dB threshold + 0x05b50006, 0x05b40044, 0x05a50001, 0x05a4001f, // Set headphone gain and Set pin1 + // to GPIO2 +}; + +const u32 pc_beep_verbs[] = { +}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/amd/mandolin/mainboard.c b/src/mainboard/amd/mandolin/mainboard.c new file mode 100644 index 0000000000..2e66c65832 --- /dev/null +++ b/src/mainboard/amd/mandolin/mainboard.c @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "gpio.h" + +/* TODO: recheck IRQ tables */ + +/* + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This table doesn't actually perform any routing. It only populates the + * PCI_INTERRUPT_LINE register on the PCI device with the PIC value specified + * in fch_apic_routing. The linux kernel only looks at this field as a backup + * if ACPI routing fails to describe the PCI routing correctly. The linux kernel + * also uses the APIC by default, so the value coded into the registers will be + * wrong. + * + * This table is also confusing because PCI Interrupt routing happens at the + * device/slot level, not the function level. + */ +static const struct pirq_struct mainboard_pirq_data[] = { + { PCIE_GPP_0_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_1_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_2_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_3_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_4_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_5_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_6_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_A_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { PCIE_GPP_B_DEVFN, { PIRQ_A, PIRQ_B, PIRQ_C, PIRQ_D } }, + { SMBUS_DEVFN, { PIRQ_SMBUS, PIRQ_NC, PIRQ_NC, PIRQ_NC } }, +}; + +static const struct fch_irq_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} mandolin_fch[] = { + { PIRQ_A, 8, 16 }, + { PIRQ_B, 10, 17 }, + { PIRQ_C, 11, 18 }, + { PIRQ_D, 12, 19 }, + { PIRQ_SCI, 9, 9 }, + { PIRQ_SD, PIRQ_NC, 16 }, + { PIRQ_SDIO, PIRQ_NC, 16 }, + { PIRQ_SATA, PIRQ_NC, 19 }, + { PIRQ_EMMC, PIRQ_NC, 17 }, + { PIRQ_GPIO, 7, 7 }, + { PIRQ_I2C2, 6, 6 }, + { PIRQ_I2C3, 14, 14 }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + { PIRQ_UART2, 4, 4 }, + { PIRQ_UART3, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_MISC1, 0x00, 0x00 }, + { PIRQ_MISC2, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_irq_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(mandolin_fch); i++) { + entry = mandolin_fch + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +static void pirq_setup(void) +{ + init_tables(); + + pirq_data_ptr = mainboard_pirq_data; + pirq_data_size = ARRAY_SIZE(mainboard_pirq_data); + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + +static void mainboard_init(void *chip_info) +{ + struct soc_amd_picasso_config *cfg = config_of_soc(); + + if (!CONFIG(PICASSO_LPC_IOMUX)) + cfg->sd_emmc_config = SD_EMMC_EMMC_HS400; + + mainboard_program_gpios(); +} + +static const fsp_pcie_descriptor pco_pcie_descriptors[] = { + { /* MXM */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 8, + .end_lane = 15, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6 + }, + { /* SSD */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5 + }, + { /* WLAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { /* LAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + }, + { /* WWAN */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 2, + .end_lane = 2, + .device_number = 1, + .function_number = 4, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ2 + }, + { /* WIFI */ + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 3, + .end_lane = 3, + .gpio_group_id = 1, + .device_number = 1, + .function_number = 5, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ3 + }, + { /* SATA EXPRESS */ + .port_present = true, + .engine_type = SATA_ENGINE, + .start_lane = 6, + .end_lane = 7, + .gpio_group_id = 1, + .channel_type = SATA_CHANNEL_LONG, + } +}; + +static const fsp_pcie_descriptor dali_pcie_descriptors[] = { + { // MXM + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 8, + .end_lane = 11, + .device_number = 1, + .function_number = 1, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ6 + }, + { // SSD + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 0, + .end_lane = 1, + .device_number = 1, + .function_number = 7, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ5 + }, + { // WLAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 4, + .end_lane = 4, + .device_number = 1, + .function_number = 2, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ0 + }, + { // LAN + .port_present = true, + .engine_type = PCIE_ENGINE, + .start_lane = 5, + .end_lane = 5, + .device_number = 1, + .function_number = 3, + .link_aspm = ASPM_L1, + .link_aspm_L1_1 = true, + .link_aspm_L1_2 = true, + .turn_off_unused_lanes = true, + .clk_req = CLK_REQ1 + } +}; + +static const fsp_ddi_descriptor pco_ddi_descriptors[] = { + { // DDI0 - DP + .connector_type = DP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { /* DDI1 - eDP */ + .connector_type = EDP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { /* DDI2 - DP */ + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + }, + { /* DDI3 - DP */ + .connector_type = DP, + .aux_index = AUX4, + .hdp_index = HDP4, + } +}; + +static const fsp_ddi_descriptor dali_ddi_descriptors[] = { + { // DDI0 - DP + .connector_type = DP, + .aux_index = AUX1, + .hdp_index = HDP1 + }, + { // DDI1 - eDP + .connector_type = EDP, + .aux_index = AUX2, + .hdp_index = HDP2 + }, + { // DDI2 - DP + .connector_type = DP, + .aux_index = AUX3, + .hdp_index = HDP3, + } +}; + +void mainboard_get_pcie_ddi_descriptors( + const fsp_pcie_descriptor **pcie_descs, size_t *pcie_num, + const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) +{ + /* Dali */ + if (soc_is_dali()) { + *pcie_descs = dali_pcie_descriptors; + *pcie_num = ARRAY_SIZE(dali_pcie_descriptors); + *ddi_descs = dali_ddi_descriptors; + *ddi_num = ARRAY_SIZE(dali_ddi_descriptors); + } + /* Picasso and default */ + else { + *pcie_descs = pco_pcie_descriptors; + *pcie_num = ARRAY_SIZE(pco_pcie_descriptors); + *ddi_descs = pco_ddi_descriptors; + *ddi_num = ARRAY_SIZE(pco_ddi_descriptors); + } +} + +static void mandolin_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = mandolin_enable, +}; diff --git a/src/mainboard/amd/mandolin/mandolin.fmd b/src/mainboard/amd/mandolin/mandolin.fmd new file mode 100644 index 0000000000..c702ba9d8b --- /dev/null +++ b/src/mainboard/amd/mandolin/mandolin.fmd @@ -0,0 +1,8 @@ +FLASH@0xFF800000 0x800000 { + BIOS@0x0 { + EC@0x0 0x21000 + RW_MRC_CACHE@0x21000 0x10000 + FMAP 0x1000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/amd/mandolin/romstage.c b/src/mainboard/amd/mandolin/romstage.c new file mode 100644 index 0000000000..853b0877b3 --- /dev/null +++ b/src/mainboard/amd/mandolin/romstage.c @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ -- cgit v1.2.3