From e1dced4561ed3b7bff98984c1d51b8e84f004b47 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 23 Sep 2017 15:40:08 +0300 Subject: amd/torpedo: Drop PlatformGnbPcieComplex.h MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Copy-paste, was not really used at all. Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21648 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer Reviewed-by: Paul Menzel Reviewed-by: Marshall Dawson --- src/mainboard/amd/torpedo/OemCustomize.c | 7 --- src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h | 60 ---------------------- 2 files changed, 67 deletions(-) delete mode 100644 src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index 196e8bbaa4..e5a3159cbe 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -13,7 +13,6 @@ * GNU General Public License for more details. */ -#include "PlatformGnbPcieComplex.h" #include #include @@ -59,12 +58,6 @@ static const PCIe_PORT_DESCRIPTOR PortList [] = { PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 7, 7), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) } - // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) -// { -// DESCRIPTOR_TERMINATE_LIST, -// PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 8, 8), -// PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) -// } }; static const PCIe_DDI_DESCRIPTOR DdiList [] = { diff --git a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h b/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h deleted file mode 100644 index ee8e4996f9..0000000000 --- a/src/mainboard/amd/torpedo/PlatformGnbPcieComplex.h +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2011 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _PLATFORM_GNB_PCIE_COMPLEX_H -#define _PLATFORM_GNB_PCIE_COMPLEX_H - -//GNB GPP Port4 -#define GNB_GPP_PORT4_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT4_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT4_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT4_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT4_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port5 -#define GNB_GPP_PORT5_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT5_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT5_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT5_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT5_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port6 -#define GNB_GPP_PORT6_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT6_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT6_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT6_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT6_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port7 -#define GNB_GPP_PORT7_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT7_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT7_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT7_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT7_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - -//GNB GPP Port8 -#define GNB_GPP_PORT8_PORT_PRESENT 1 //0:Disable 1:Enable -#define GNB_GPP_PORT8_SPEED_MODE 2 //0:Auto 1:GEN1 2:GEN2 -#define GNB_GPP_PORT8_LINK_ASPM 3 //0:Disable 1:L0s 2:L1 3:L0s+L1 -#define GNB_GPP_PORT8_CHANNEL_TYPE 4 //0:LowLoss(-3.5db) 1:HighLoss(-6db) 2:Half-swing(0db) - //3:Half-swing(-3.5db) 4:extended length (-6db) 5:extended length(-8db) -#define GNB_GPP_PORT8_HOTPLUG_SUPPORT 0 //0:Disable 1:Basic 3:Enhanced - - -#endif //_PLATFORM_GNB_PCIE_COMPLEX_H -- cgit v1.2.3