From d9a634c7560d0af50e141ad18ffc8c48519209e7 Mon Sep 17 00:00:00 2001 From: Scott Duplichan Date: Sun, 15 May 2011 21:51:31 +0000 Subject: Switch processor cores to pstate 0 early to reduce boot time. Signed-off-by: Scott Duplichan Acked-by: Marc Jones git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6583 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/persimmon/romstage.c | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/persimmon/romstage.c b/src/mainboard/amd/persimmon/romstage.c index 51e7a8df1f..e3ed847fdb 100644 --- a/src/mainboard/amd/persimmon/romstage.c +++ b/src/mainboard/amd/persimmon/romstage.c @@ -47,6 +47,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u32 val; u8 reg8; + // all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time + __writemsr (0xc0010062, 0); + // early enable of SPI 33 MHz fast mode read if (boot_cpu()) { -- cgit v1.2.3