From bc21a41e1ca045baae57f79d89aafdf682528a4b Mon Sep 17 00:00:00 2001
From: Dave Frodin <dave.frodin@se-eng.com>
Date: Mon, 19 Jan 2015 11:40:38 -0700
Subject: southbridge/amd/pi: Rename Avalon to Hudson

To maintain consistancy with southbridge/amd/agesa/hudson rename
pi/avalon to pi/hudson in advance of adding support for the
base hudson southbridge.

Change-Id: Icff8c4c06aae2d40cbd9e90903754735ac3510c3
Signed-off-by: Dave Frodin <dave.frodin@se-eng.com>
Reviewed-on: http://review.coreboot.org/8251
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
---
 src/mainboard/amd/olivehillplus/devicetree.cb |  4 ++--
 src/mainboard/amd/olivehillplus/dsdt.asl      | 10 +++++-----
 src/mainboard/amd/olivehillplus/mptable.c     |  2 +-
 src/mainboard/amd/olivehillplus/romstage.c    |  2 +-
 4 files changed, 9 insertions(+), 9 deletions(-)

(limited to 'src/mainboard/amd')

diff --git a/src/mainboard/amd/olivehillplus/devicetree.cb b/src/mainboard/amd/olivehillplus/devicetree.cb
index 65f7ee4577..8dd067128f 100644
--- a/src/mainboard/amd/olivehillplus/devicetree.cb
+++ b/src/mainboard/amd/olivehillplus/devicetree.cb
@@ -41,7 +41,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 				device pci 8.0 on  end # Platform Security Processor
 			end	#chip northbridge/amd/pi/00730F01
 
-			chip southbridge/amd/pi/avalon # it is under NB/SB Link, but on the same pci bus
+			chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus
 				device pci 10.0 on  end # XHCI HC0
 				device pci 11.0 on  end # SATA
 				device pci 12.0 on  end # USB
@@ -60,7 +60,7 @@ chip northbridge/amd/pi/00730F01/root_complex
 				device pci 14.3 on  end # LPC	0x439d
 				device pci 14.7 on  end # SD
 				device pci 16.0 on  end # USB
-			end	#chip southbridge/amd/pi/avalon
+			end	#chip southbridge/amd/pi/hudson
 
 			device pci 18.0 on  end
 			device pci 18.1 on  end
diff --git a/src/mainboard/amd/olivehillplus/dsdt.asl b/src/mainboard/amd/olivehillplus/dsdt.asl
index 56381e18f3..68ed74e84a 100644
--- a/src/mainboard/amd/olivehillplus/dsdt.asl
+++ b/src/mainboard/amd/olivehillplus/dsdt.asl
@@ -37,13 +37,13 @@ DefinitionBlock (
 	#include "acpi/usb_oc.asl"
 
 	/* PCI IRQ mapping for the Southbridge */
-	#include <southbridge/amd/pi/avalon/acpi/pcie.asl>
+	#include <southbridge/amd/pi/hudson/acpi/pcie.asl>
 
 	/* Describe the processor tree (\_PR) */
 	#include <cpu/amd/pi/00730F01/acpi/cpu.asl>
 
 	/* Contains the supported sleep states for this chipset */
-	#include <southbridge/amd/pi/avalon/acpi/sleepstates.asl>
+	#include <southbridge/amd/pi/hudson/acpi/sleepstates.asl>
 
 	/* Contains the Sleep methods (WAK, PTS, GTS, etc.) */
 	#include "acpi/sleep.asl"
@@ -68,16 +68,16 @@ DefinitionBlock (
 			#include <northbridge/amd/pi/00730F01/acpi/northbridge.asl>
 
 			/* Describe the AMD Fusion Controller Hub Southbridge */
-			#include <southbridge/amd/pi/avalon/acpi/fch.asl>
+			#include <southbridge/amd/pi/hudson/acpi/fch.asl>
 		}
 
 		/* Describe PCI INT[A-H] for the Southbridge */
-		#include <southbridge/amd/pi/avalon/acpi/pci_int.asl>
+		#include <southbridge/amd/pi/hudson/acpi/pci_int.asl>
 
 	} /* End \_SB scope */
 
 	/* Describe SMBUS for the Southbridge */
-	#include <southbridge/amd/pi/avalon/acpi/smbus.asl>
+	#include <southbridge/amd/pi/hudson/acpi/smbus.asl>
 
 	/* Define the General Purpose Events for the platform */
 	#include "acpi/gpe.asl"
diff --git a/src/mainboard/amd/olivehillplus/mptable.c b/src/mainboard/amd/olivehillplus/mptable.c
index 80ba5b5af7..d49c998332 100644
--- a/src/mainboard/amd/olivehillplus/mptable.c
+++ b/src/mainboard/amd/olivehillplus/mptable.c
@@ -27,7 +27,7 @@
 #include <cpu/amd/amdfam15.h>
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/avalon/hudson.h> /* pm_ioread() */
+#include <southbridge/amd/pi/hudson/hudson.h> /* pm_ioread() */
 
 u8 picr_data[0x54] = {
 	0x03,0x04,0x05,0x07,0x0B,0x0A,0x1F,0x1F,0xFA,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F,
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 63044ed4d0..6b081c653e 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -34,7 +34,7 @@
 #include <northbridge/amd/pi/agesawrapper_call.h>
 #include <cpu/x86/bist.h>
 #include <cpu/x86/lapic.h>
-#include <southbridge/amd/pi/avalon/hudson.h>
+#include <southbridge/amd/pi/hudson/hudson.h>
 #include <cpu/amd/pi/s3_resume.h>
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-- 
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