From aeb85d53e90728bf758b08895c7ed5dbf9cf3062 Mon Sep 17 00:00:00 2001
From: Kyösti Mälkki <kyosti.malkki@gmail.com>
Date: Fri, 29 Nov 2019 06:37:52 +0200
Subject: binaryPI: Clean leftover romstage prototype
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Change-Id: Ie9e7a88f1f8dce967772e7c5ecf4aea971bb1c3f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37346
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/mainboard/amd/bettong/romstage.c       | 3 +--
 src/mainboard/amd/db-ft3b-lc/romstage.c    | 6 +++---
 src/mainboard/amd/lamar/romstage.c         | 3 +--
 src/mainboard/amd/olivehillplus/romstage.c | 3 +--
 4 files changed, 6 insertions(+), 9 deletions(-)

(limited to 'src/mainboard/amd')

diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c
index 32f52de707..03e6585b9a 100644
--- a/src/mainboard/amd/bettong/romstage.c
+++ b/src/mainboard/amd/bettong/romstage.c
@@ -19,11 +19,10 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/bist.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c
index 495ce59eff..2979cf4ae4 100644
--- a/src/mainboard/amd/db-ft3b-lc/romstage.c
+++ b/src/mainboard/amd/db-ft3b-lc/romstage.c
@@ -19,13 +19,13 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{	u32 val;
+static void romstage_main_template(void)
+{
+	u32 val;
 
 	/*
 	 *  In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c
index 77a0ea02f7..67485f4f11 100644
--- a/src/mainboard/amd/lamar/romstage.c
+++ b/src/mainboard/amd/lamar/romstage.c
@@ -19,7 +19,6 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/common/amd_defs.h>
@@ -28,7 +27,7 @@
 
 #define SERIAL_DEV PNP_DEV(0x4e, F81216H_SP1)
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 
diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c
index 6df12e31cc..519825827a 100644
--- a/src/mainboard/amd/olivehillplus/romstage.c
+++ b/src/mainboard/amd/olivehillplus/romstage.c
@@ -19,12 +19,11 @@
 #include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
-#include <cpu/amd/car.h>
 #include <northbridge/amd/agesa/state_machine.h>
 #include <cpu/x86/bist.h>
 #include <southbridge/amd/pi/hudson/hudson.h>
 
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+static void romstage_main_template(void)
 {
 	u32 val;
 
-- 
cgit v1.2.3