From 9fee35c6c4aafd0f8c429263e24a7378dc138f02 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sat, 23 Sep 2017 19:10:04 +0300 Subject: AGESA: Split long lines in OemCustomize.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I907f55622e6aaba401471239f706ab24cd26319f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/21651 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones --- src/mainboard/amd/inagua/OemCustomize.c | 24 +++++++++++--- src/mainboard/amd/parmer/OemCustomize.c | 43 +++++++++++++++++++++----- src/mainboard/amd/persimmon/OemCustomize.c | 30 +++++++++++++++--- src/mainboard/amd/south_station/OemCustomize.c | 30 +++++++++++++++--- src/mainboard/amd/thatcher/OemCustomize.c | 42 ++++++++++++++++++++----- src/mainboard/amd/torpedo/OemCustomize.c | 36 +++++++++++++++++---- src/mainboard/amd/union_station/OemCustomize.c | 30 +++++++++++++++--- 7 files changed, 195 insertions(+), 40 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/inagua/OemCustomize.c b/src/mainboard/amd/inagua/OemCustomize.c index 5fc293b791..fa2d7e4b51 100644 --- a/src/mainboard/amd/inagua/OemCustomize.c +++ b/src/mainboard/amd/inagua/OemCustomize.c @@ -23,25 +23,41 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 4) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) PCIE LAN { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 6) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) MINIPCIE SLOT1 { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 7) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) } }; diff --git a/src/mainboard/amd/parmer/OemCustomize.c b/src/mainboard/amd/parmer/OemCustomize.c index 21847f91a7..0a0fe7545e 100644 --- a/src/mainboard/amd/parmer/OemCustomize.c +++ b/src/mainboard/amd/parmer/OemCustomize.c @@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 23), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 4, PCI Device Number 4, PCIE MINI0 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 6, PCI Device Number 6, PCIE SLOT1 x1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 7, PCI Device Number 7, LAN */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) }, }; @@ -131,7 +159,6 @@ static const PCIe_DDI_DESCRIPTOR DdiList[] = { { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PcieDdiEngine, 32, 35), - /* PCIE_DDI_DATA_INITIALIZER(ConnectorTypeEDP, Aux3, Hdp3) */ PCIE_DDI_DATA_INITIALIZER(ConnectorTypeDP, Aux3, Hdp3) }, }; diff --git a/src/mainboard/amd/persimmon/OemCustomize.c b/src/mainboard/amd/persimmon/OemCustomize.c index a666de098f..a646e38691 100644 --- a/src/mainboard/amd/persimmon/OemCustomize.c +++ b/src/mainboard/amd/persimmon/OemCustomize.c @@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 46) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 46) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 46) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 46) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) } }; diff --git a/src/mainboard/amd/south_station/OemCustomize.c b/src/mainboard/amd/south_station/OemCustomize.c index c90feb1d02..45c9f11d57 100644 --- a/src/mainboard/amd/south_station/OemCustomize.c +++ b/src/mainboard/amd/south_station/OemCustomize.c @@ -23,31 +23,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 4) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 6) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 7) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) } }; diff --git a/src/mainboard/amd/thatcher/OemCustomize.c b/src/mainboard/amd/thatcher/OemCustomize.c index c035722c58..a6c98b9026 100644 --- a/src/mainboard/amd/thatcher/OemCustomize.c +++ b/src/mainboard/amd/thatcher/OemCustomize.c @@ -69,48 +69,76 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 15, 8), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 16:23, PCI Device Number 3, Disabled */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PcieUnusedEngine, 16, 23), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 4, PCI Device Number 4, LAN */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 5, PCI Device Number 5, PCIE MINI0 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 6, PCI Device Number 6, PCIE MINI1 */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 7, PCI Device Number 7, Disabled */ { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 1) + PCIE_PORT_DATA_INITIALIZER(PortDisabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 1) }, /* PCIe port, Lanes 0:3, PCI Device Number 8, Bridge to FCH */ { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) }, }; diff --git a/src/mainboard/amd/torpedo/OemCustomize.c b/src/mainboard/amd/torpedo/OemCustomize.c index bb377fa3c6..1ad6cde9db 100644 --- a/src/mainboard/amd/torpedo/OemCustomize.c +++ b/src/mainboard/amd/torpedo/OemCustomize.c @@ -22,37 +22,61 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 8, 15), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT2) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, BIT2) }, // Initialize Port descriptor (PCIe port, Lanes 16:19, PCI Device Number 3, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 16, 19), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, BIT3) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, BIT3) }, // Initialize Port descriptor (PCIe port, Lanes 4, PCI Device Number 4, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmDisabled, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, 0) } }; diff --git a/src/mainboard/amd/union_station/OemCustomize.c b/src/mainboard/amd/union_station/OemCustomize.c index 43b2521097..d266d277f0 100644 --- a/src/mainboard/amd/union_station/OemCustomize.c +++ b/src/mainboard/amd/union_station/OemCustomize.c @@ -24,31 +24,51 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 4), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 4) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 4, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 4) }, // Initialize Port descriptor (PCIe port, Lanes 5, PCI Device Number 5, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 5, 5), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 5) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 5, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 5) }, // Initialize Port descriptor (PCIe port, Lanes 6, PCI Device Number 6, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 6, 6), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 6) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 6, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 6) }, // Initialize Port descriptor (PCIe port, Lanes 7, PCI Device Number 7, ...) { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 7, 7), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 7) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 7, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 7) }, // Initialize Port descriptor (PCIe port, Lanes 8, PCI Device Number 8, ...) { DESCRIPTOR_TERMINATE_LIST, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 3), - PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, HotplugDisabled, PcieGen2, PcieGen2, AspmL0sL1, 0) + PCIE_PORT_DATA_INITIALIZER(PortEnabled, ChannelTypeExt6db, 8, + HotplugDisabled, + PcieGen2, + PcieGen2, + AspmL0sL1, 0) } }; -- cgit v1.2.3