From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/db800/romstage.c | 3 +-- src/mainboard/amd/dbm690t/romstage.c | 4 +--- src/mainboard/amd/mahogany/romstage.c | 4 +--- src/mainboard/amd/mahogany_fam10/romstage.c | 6 +----- src/mainboard/amd/norwich/romstage.c | 3 +-- src/mainboard/amd/pistachio/romstage.c | 4 +--- src/mainboard/amd/rumba/romstage.c | 4 +--- src/mainboard/amd/serengeti_cheetah/romstage.c | 11 +---------- src/mainboard/amd/tilapia_fam10/romstage.c | 6 +----- 9 files changed, 9 insertions(+), 36 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 0f2ec7fce0..8977b27bd4 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -30,6 +30,7 @@ #include #include #include "southbridge/amd/cs5536/cs5536.h" +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -45,8 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE60EE -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 8c8978785c..94d4fc457a 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include @@ -43,6 +40,7 @@ #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" +#include #include diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 39e6675496..d4d70abcea 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -20,9 +20,6 @@ #define RC0 (6<<8) #define RC1 (7<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 - #define SMBUS_HUB 0x71 #include @@ -34,6 +31,7 @@ #include #include #include +#include #include #include "northbridge/amd/amdk8/raminit.h" diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 3e6466e72c..abb2a114f8 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -57,6 +57,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "southbridge/amd/rs780/rs780_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c" +#include static void activate_spd_rom(const struct mem_controller *ctrl) { @@ -90,11 +91,6 @@ static int spd_read_byte(u32 device, u32 address) #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index e957d7ea94..1211610421 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -30,6 +30,7 @@ #include #include #include "southbridge/amd/cs5536/cs5536.h" +#include #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" @@ -42,8 +43,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x00001490 /* manual settings for the PLL */ #define PLLMSRlo 0x02000030 -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 740b148f7e..f1f61c3d0c 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define DIMM0 0x50 -#define DIMM1 0x51 - #include #include #include @@ -39,6 +36,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include "superio/ite/it8712f/it8712f_early_serial.c" #include +#include #include "cpu/x86/mtrr/earlymtrr.c" #include "cpu/x86/bist.h" diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index f8cd775f02..e08d967471 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -9,15 +9,13 @@ #include "cpu/x86/msr.h" #include #include +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #include "southbridge/amd/cs5536/cs5536_early_smbus.c" #include "southbridge/amd/cs5536/cs5536_early_setup.c" -#define DIMM0 0xA0 -#define DIMM1 0xFF /* DIMM1 is not available/used on this board. */ - static inline int spd_read_byte(unsigned device, unsigned address) { if (device != DIMM0) diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index 24a4bf44f8..40f6b7be1c 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -92,22 +92,13 @@ static inline int spd_read_byte(unsigned device, unsigned address) #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" +#include #define RC0 ((1<<0)<<8) #define RC1 ((1<<1)<<8) #define RC2 ((1<<2)<<8) #define RC3 ((1<<3)<<8) -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 -#define DIMM4 0x54 -#define DIMM5 0x55 -#define DIMM6 0x56 -#define DIMM7 0x57 - - #include "cpu/amd/car/post_cache_as_ram.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index eef7c8c466..c73a07c357 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -84,17 +84,13 @@ static int spd_read_byte(u32 device, u32 address) #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" +#include //#include "spd_addr.h" #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -- cgit v1.2.3