From 8d313685b094f0ffa020e5707c5857b1a2063d28 Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Wed, 5 May 2010 13:12:42 +0000 Subject: Rename "apic" and "apic_cluster" to "lapic" and "lapic_cluster" in device trees. Adapt sconfig as necessary. Signed-off-by: Patrick Georgi Acked-by: Stefan Reinauer Acked-by: Peter Stuge git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5525 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/db800/devicetree.cb | 4 ++-- src/mainboard/amd/dbm690t/devicetree.cb | 4 ++-- src/mainboard/amd/mahogany/devicetree.cb | 4 ++-- src/mainboard/amd/mahogany_fam10/devicetree.cb | 4 ++-- src/mainboard/amd/norwich/devicetree.cb | 4 ++-- src/mainboard/amd/pistachio/devicetree.cb | 4 ++-- src/mainboard/amd/rumba/devicetree.cb | 4 ++-- src/mainboard/amd/serengeti_cheetah/devicetree.cb | 4 ++-- src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb | 4 ++-- src/mainboard/amd/tilapia_fam10/devicetree.cb | 4 ++-- 10 files changed, 20 insertions(+), 20 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/db800/devicetree.cb b/src/mainboard/amd/db800/devicetree.cb index d79fb51c2c..e872571194 100644 --- a/src/mainboard/amd/db800/devicetree.cb +++ b/src/mainboard/amd/db800/devicetree.cb @@ -59,9 +59,9 @@ chip northbridge/amd/lx end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end diff --git a/src/mainboard/amd/dbm690t/devicetree.cb b/src/mainboard/amd/dbm690t/devicetree.cb index a12e82db13..f6ed959293 100644 --- a/src/mainboard/amd/dbm690t/devicetree.cb +++ b/src/mainboard/amd/dbm690t/devicetree.cb @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_S1G1 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb index 19979a2e91..d09fdd0238 100644 --- a/src/mainboard/amd/mahogany/devicetree.cb +++ b/src/mainboard/amd/mahogany/devicetree.cb @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb index 8478ac1165..d73e07933c 100644 --- a/src/mainboard/amd/mahogany_fam10/devicetree.cb +++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb @@ -1,8 +1,8 @@ # sample config for amd/mahogany_fam10 chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2r2 #L1 and DDR2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/norwich/devicetree.cb b/src/mainboard/amd/norwich/devicetree.cb index bc08b95954..533ea92b2d 100644 --- a/src/mainboard/amd/norwich/devicetree.cb +++ b/src/mainboard/amd/norwich/devicetree.cb @@ -32,9 +32,9 @@ chip northbridge/amd/lx end end # APIC cluster is late CPU init. - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_lx - device apic 0 on end + device lapic 0 on end end end end diff --git a/src/mainboard/amd/pistachio/devicetree.cb b/src/mainboard/amd/pistachio/devicetree.cb index 139a17e836..435e03b2c2 100644 --- a/src/mainboard/amd/pistachio/devicetree.cb +++ b/src/mainboard/amd/pistachio/devicetree.cb @@ -9,9 +9,9 @@ #Define gfx_reconfiguration, 0: short reconfiguration, 1(default): long reconfiguration #Define gfx_link_width, 0: x16, 1: x1, 2: x2, 3: x4, 4: x8, 5: x12 (not supported), 6: x16 chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb index bc84dc0373..ac4f4b494d 100644 --- a/src/mainboard/amd/rumba/devicetree.cb +++ b/src/mainboard/amd/rumba/devicetree.cb @@ -1,9 +1,9 @@ chip northbridge/amd/gx2 register "setupflash" = "0" #register "irqmap" = "0xaa5b" - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/model_gx2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/serengeti_cheetah/devicetree.cb b/src/mainboard/amd/serengeti_cheetah/devicetree.cb index c1748697f4..8ea682fa5a 100644 --- a/src/mainboard/amd/serengeti_cheetah/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah/devicetree.cb @@ -1,7 +1,7 @@ chip northbridge/amd/amdk8/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb index 71c4daafc1..7c36509bf8 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb +++ b/src/mainboard/amd/serengeti_cheetah_fam10/devicetree.cb @@ -1,7 +1,7 @@ chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_F_1207 #L1 and DDR2 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on diff --git a/src/mainboard/amd/tilapia_fam10/devicetree.cb b/src/mainboard/amd/tilapia_fam10/devicetree.cb index 63b1d49f0f..c725aaae26 100644 --- a/src/mainboard/amd/tilapia_fam10/devicetree.cb +++ b/src/mainboard/amd/tilapia_fam10/devicetree.cb @@ -1,8 +1,8 @@ # sample config for amd/tilapia_fam10 chip northbridge/amd/amdfam10/root_complex - device apic_cluster 0 on + device lapic_cluster 0 on chip cpu/amd/socket_AM3 #L1 and DDR3 - device apic 0 on end + device lapic 0 on end end end device pci_domain 0 on -- cgit v1.2.3