From 81998090792ebc1a6e39455f5fcb4d2c9ec9c095 Mon Sep 17 00:00:00 2001 From: Edward O'Callaghan Date: Mon, 28 Apr 2014 18:07:33 +1000 Subject: mainboard/: Avoid including early_serial.c from w83627hf Following the reasoning of: dbbc136 mainboard/asrock/e350m1: Avoid including early_serial.c Change-Id: I5d729b90cf6713de2674fb00c726cd2944a3ab4e Signed-off-by: Edward O'Callaghan Reviewed-on: http://review.coreboot.org/5597 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/amd/db800/romstage.c | 5 +++-- src/mainboard/amd/rumba/Kconfig | 1 + src/mainboard/amd/rumba/romstage.c | 5 +++-- src/mainboard/amd/serengeti_cheetah/romstage.c | 7 ++++--- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 5 +++-- 5 files changed, 14 insertions(+), 9 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 93fc0e53aa..564380e711 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -32,7 +32,8 @@ #include #include "southbridge/amd/cs5536/early_smbus.c" #include "southbridge/amd/cs5536/early_setup.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include +#include #include "northbridge/amd/lx/raminit.h" #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -63,7 +64,7 @@ void main(unsigned long bist) /* Note: must do this AFTER the early_setup! It is counting on some * early MSR setup for CS5536. */ - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ diff --git a/src/mainboard/amd/rumba/Kconfig b/src/mainboard/amd/rumba/Kconfig index d600a588a4..1d60d0c35c 100644 --- a/src/mainboard/amd/rumba/Kconfig +++ b/src/mainboard/amd/rumba/Kconfig @@ -24,6 +24,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_AMD_GEODE_GX2 select NORTHBRIDGE_AMD_GX2 select SOUTHBRIDGE_AMD_CS5536 + select SUPERIO_WINBOND_W83627HF select UDELAY_TSC select HAVE_PIRQ_TABLE select BOARD_ROMSIZE_KB_256 diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index cec7c3698b..c5a3fc3a7c 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -4,7 +4,8 @@ #include #include #include -#include "superio/winbond/w83627hf/early_serial.c" +#include +#include #include "cpu/x86/bist.h" #include "cpu/x86/msr.h" #include @@ -38,7 +39,7 @@ void main(unsigned long bist) SystemPreInit(); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); cs5536_early_setup(); diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index b103389c63..14320a562c 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -15,7 +15,8 @@ #include "lib/delay.c" #include "northbridge/amd/amdk8/debug.c" #include -#include "superio/winbond/w83627hf/early_serial.c" +#include +#include #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -113,8 +114,8 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - console_init(); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index bb7d5d333b..09b86bb9e2 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -44,7 +44,8 @@ #include #include "cpu/x86/bist.h" #include "northbridge/amd/amdfam10/debug.c" -#include "superio/winbond/w83627hf/early_serial.c" +#include +#include #include "northbridge/amd/amdfam10/setup_resource_map.c" #include "southbridge/amd/amd8111/early_ctrl.c" @@ -204,7 +205,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x32); - w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); -- cgit v1.2.3