From 7f94b405be122b85438f4cd17aa1d43a106b987f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 17 Aug 2020 20:00:31 +0200 Subject: mb/amd/mandolin: enable SoC UARTs 0 and 1 and disable 2 and 3 There are only headers for the SoC's UART 0 and 1 on the board. BUG=b:165020060 TEST=Linux only detects UART 0 and 1. Change-Id: I45929f65a5f844ae5cef792b11176f487c80766f Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/44530 Reviewed-by: Raul Rangel Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb index ffc18a0d69..0004ecd266 100644 --- a/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb +++ b/src/mainboard/amd/mandolin/variants/mandolin/devicetree.cb @@ -155,4 +155,10 @@ chip soc/amd/picasso device pci 18.6 on end device pci 18.7 on end end # domain + + device mmio 0xfedc9000 on end # UART0 + device mmio 0xfedca000 on end # UART1 + device mmio 0xfedce000 off end # UART2 + device mmio 0xfedcf000 off end # UART3 + end # chip soc/amd/picasso -- cgit v1.2.3