From 798ef2893c44ce3194c539c8c5db33d11e8edbac Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Mon, 29 Mar 2010 22:08:01 +0000 Subject: This drops the ASSEMBLY define from romstage.c, too (since it's not assembly code, this was a dirty hack anyways) Also run awk 1 RS= ORS="\n\n" < $FILE > $FILE.nonewlines mv $FILE.nonewlines $FILE on romstage.c because my perl -pi -e 's,#define ASSEMBLY 1,,g' */*/romstage.c cut some holes into the source. Signed-off-by: Stefan Reinauer Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5320 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/db800/romstage.c | 5 +---- src/mainboard/amd/dbm690t/romstage.c | 5 +---- src/mainboard/amd/mahogany/romstage.c | 4 +--- src/mainboard/amd/mahogany_fam10/romstage.c | 12 +----------- src/mainboard/amd/norwich/romstage.c | 3 +-- src/mainboard/amd/pistachio/romstage.c | 4 +--- src/mainboard/amd/rumba/romstage.c | 5 +---- src/mainboard/amd/serengeti_cheetah/romstage.c | 8 +------- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 17 ----------------- 9 files changed, 8 insertions(+), 55 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 640dc4984f..1547dc4da3 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -18,9 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #include #include #include @@ -87,7 +84,6 @@ static const struct msrinit msr_table[] = {MSR_GLIU1_SHADOW, {.hi = 0x2000FFFF,.lo = 0xFFFF0003}}, // 0xC0000-0xFFFFF }; - static void msr_init(void) { int i; @@ -133,3 +129,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 872cb2f0a3..8decf4c7c2 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -179,7 +176,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) rs690_htinit(); printk(BIOS_DEBUG, "needs_reset=0x%x\n", needs_reset); - if (needs_reset) { print_info("ht reset -\r\n"); soft_reset(); @@ -198,3 +194,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 0c25cf6b77..f9ca92fac1 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -196,3 +193,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index f9259cd43a..332e256085 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -17,15 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - - //#define SYSTEM_TYPE 0 /* SERVER */ #define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 1 @@ -71,7 +66,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #define printk(BIOS_INFO, fmt, arg...) do_printk(BIOS_INFO ,fmt, ##arg) #include "cpu/x86/bist.h" - static int smbus_read_byte(u32 device, u32 address); #include "superio/ite/it8718f/it8718f_early_serial.c" @@ -86,17 +80,14 @@ static void memreset_setup(void) { } - static void memreset(int controllers, const struct mem_controller *ctrl) { } - static void activate_spd_rom(const struct mem_controller *ctrl) { } - static int spd_read_byte(u32 device, u32 address) { int result; @@ -118,7 +109,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" - #include "northbridge/amd/amdfam10/early_ht.c" #include "southbridge/amd/sb700/sb700_early_setup.c" @@ -281,7 +271,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); rs780_before_pci_init(); @@ -292,3 +281,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. } + diff --git a/src/mainboard/amd/norwich/romstage.c b/src/mainboard/amd/norwich/romstage.c index 19c5b17ade..6337e89c2c 100644 --- a/src/mainboard/amd/norwich/romstage.c +++ b/src/mainboard/amd/norwich/romstage.c @@ -18,8 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - #include #include #include @@ -132,3 +130,4 @@ void cache_as_ram_main(void) /* Memory is setup. Return to cache_as_ram.inc and continue to boot. */ return; } + diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index e38c63916c..d4dcca3822 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -17,9 +17,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define K8_SET_FIDVID 1 #define QRANK_DIMM_SUPPORT 1 @@ -208,3 +205,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); } + diff --git a/src/mainboard/amd/rumba/romstage.c b/src/mainboard/amd/rumba/romstage.c index ea3ec908fa..087fe1842a 100644 --- a/src/mainboard/amd/rumba/romstage.c +++ b/src/mainboard/amd/rumba/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #include #include #include @@ -118,7 +115,6 @@ static void msr_init(void) /* put code in northbridge[init].c here */ } - static void main(unsigned long bist) { static const struct mem_controller memctrl [] = { @@ -146,3 +142,4 @@ static void main(unsigned long bist) /* Check all of memory */ //ram_check(0x00000000, 640*1024); } + diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index d4d3c46c0c..247e920b95 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -1,6 +1,3 @@ -#define ASSEMBLY 1 - - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 0 @@ -32,7 +29,6 @@ #include "option_table.h" #include "pc80/mc146818rtc_early.c" - #if 0 static void post_code(uint8_t value) { #if 1 @@ -50,8 +46,6 @@ static void post_code(uint8_t value) { #include "northbridge/amd/amdk8/raminit.h" #include "cpu/amd/model_fxx/apic_timer.c" - - #include "cpu/x86/lapic/boot_cpu.c" #include "northbridge/amd/amdk8/reset_test.c" @@ -142,7 +136,6 @@ static inline int spd_read_byte(unsigned device, unsigned address) #define DIMM6 0x56 #define DIMM7 0x57 - #include "cpu/amd/car/copy_and_run.c" #include "cpu/amd/car/post_cache_as_ram.c" @@ -330,3 +323,4 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now } + diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index e628304445..4d86535bbe 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -17,15 +17,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ - -#define ASSEMBLY 1 - - #define SYSTEM_TYPE 0 /* SERVER */ //#define SYSTEM_TYPE 1 /* DESKTOP */ //#define SYSTEM_TYPE 2 /* MOBILE */ - #define RAMINIT_SYSINFO 1 #define CACHE_AS_RAM_ADDRESS_DEBUG 1 @@ -71,7 +66,6 @@ int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, #endif #include "cpu/x86/bist.h" - #include "northbridge/amd/amdfam10/debug.c" #include "superio/winbond/w83627hf/w83627hf_early_serial.c" #include "cpu/amd/mtrr/amd_earlymtrr.c" @@ -87,12 +81,10 @@ static void memreset_setup(void) outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 17); } - static void memreset(int controllers, const struct mem_controller *ctrl) { } - static void activate_spd_rom(const struct mem_controller *ctrl) { #define SMBUS_HUB 0x18 @@ -109,7 +101,6 @@ static void activate_spd_rom(const struct mem_controller *ctrl) smbus_write_byte(SMBUS_HUB, 0x03, 0); } - static int spd_read_byte(u32 device, u32 address) { int result; @@ -131,7 +122,6 @@ static int spd_read_byte(u32 device, u32 address) #include "cpu/amd/model_10xxx/init_cpus.c" #include "cpu/amd/model_10xxx/fidvid.c" - #include "southbridge/amd/amd8111/amd8111_enable_rom.c" #include "northbridge/amd/amdfam10/early_ht.c" @@ -244,7 +234,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); #endif - /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); @@ -254,7 +243,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x3B); - /* FIXME: Move this to chipset init. enable cf9 for hard reset */ print_debug("enable_cf9_x()\n"); @@ -266,12 +254,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); - printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); post_code(0x3E); - memreset_setup(); post_code(0x40); @@ -281,7 +267,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) raminit_amdmct(sysinfo); post_code(0x41); - /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); @@ -292,7 +277,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // ram_check(0x00200000, 0x00200000 + (640 * 1024)); // ram_check(0x40200000, 0x40200000 + (640 * 1024)); - // die("After MCT init before CAR disabled."); post_code(0x42); @@ -300,6 +284,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. - } -- cgit v1.2.3